Himax Technologies, Inc.

Hung-Yu Huang

Jia-Hui Wang

Chuan-Chien Hsu

Chin-Tien Chang

Shu-Ming Chang

Chen-Yu Wang

Tsung-Yi Tsai

Siangwei Wang

Sheng-Wen Huang

Shiang-Wei Wang

Chia-Hui Wang

A method of performing power saving control on a display device includes: generating, by a timing controller of the display device, a power saving start indication and a power saving end indication in response to changing of a refresh rate of the display device; receiving, by a source driver of the display device, the power saving start indication and the power saving end indication; in response to the power saving start indication, allowing a part of circuitry of the source driver to be powered down during a vertical blanking interval; and in response to the power saving end indication, allowing the powered down part of circuitry of the source driver to be woken up during the vertical blanking interval.

Method of performing power saving control on display device and related display device

A source driver and a polarity inversion control circuit are provided. The source driver includes a plurality of channel pairs and the polarity inversion control circuit. The polarity inversion control circuit includes a signal generating circuit and a routing circuit. The signal generating circuit generates a polarity control signal. The routing circuit outputs a plurality of switching control signals corresponding to the polarity control signal to a plurality of output switching circuits of the channel pairs. The routing circuit changes the correspondence between the polarity control signal and the switching control signals according to a polarity inversion configuration signal.

Source driver and polarity inversion control circuit

An output amplifier of a source driver and a control method thereof are provided. The output amplifier includes a first switch circuit, a second switch circuit, a third switch circuit, a first input stage circuit, a second input stage circuit, a first active load circuit, a second active load circuit, a first positive output stage circuit, a first negative output stage circuit, a second positive output stage circuit and a second negative output stage circuit. In a first display stage of the control method, the first switch circuit outputs a positive reference signal through a first output terminal and outputs a negative reference signal through a second output terminal. In a second display stage of the control method, the signals outputted by the first output terminal and the second output terminal are exchanged.

Output amplifier of a source driver and control method thereof

A driving apparatus and a method for driving a display panel thereof are provided. The driving apparatus includes an output buffer, a switch, an adjusting circuit, a digital-to-analog converter and a code detecting unit. The output buffer provides an output voltage to a load according to a static current determining a speed of the output voltage reaching a target voltage for driving the load. The switch is coupled between the output buffer and the load in series, and is turned on or off according to a control signal. The code detecting unit detects an input code. The adjusting circuit determines whether the input code varies when the control signal is enabled, and disables a high driving ratio signal when the input code does not vary when the control signal is enabled. An enabling period of the high driving ratio signal is different from an enabling period of the control signal.

Driving apparatus and method for driving display panel thereof

A circuit and a calibrating method are provided. A pixel sensor senses a terminal voltage of a driving transistor during a sensing period. A calibration sensor senses a first predetermined voltage and a second predetermined voltage during a calibration period. An amplifying circuit amplifies the terminal voltage according to a gain, and amplifies the first predetermined voltage and the second predetermined voltage according to the gain. An analog to digital converter converts the amplified terminal voltage into a digital code, and converts the amplified first predetermined voltage into a first digital code and converts the amplified second predetermined voltage into a second digital code. A gain adjusting circuit adjusts the gain according to the first digital code and the second digital code. Accordingly, the gain of the amplifying circuit is calibrated.

Calibrating circuit and calibrating method for display panel

A voltage sensing circuit is provided. The voltage sensing circuit includes two differential amplifiers and a buffer. The first differential amplifier receives a first input voltage and a first reference voltage and provides a first current and a second current according to the difference between the first input voltage and the first reference voltage. The second differential amplifier receives a second input voltage and a second reference voltage and provides a third current and a fourth current according to the difference between the second input voltage and the second reference voltage. The buffer is coupled to the two differential amplifiers. The buffer generates an output voltage based on the first current, the second current, the third current, and the fourth current.

Voltage sensing circuit

A gamma operational amplifier circuit, a source driver, and a method for eliminating voltage offset are disclosed. The gamma operational amplifier circuit includes a first switch circuit, a second switch circuit, a first operational amplifier and a second operational amplifier. The source driver includes the gamma operational amplifier circuit, a resistor string and a digital-to-analog converter. The method for eliminating voltage offset includes a positive polarity control stage and a negative polarity control stage. In the method for eliminating voltage offset, the positive polarity control stage and the negative polarity control stage control the first switch circuit and the second switch circuit to change paths at which a first reference voltage and a second reference voltage pass through to enable the first reference voltage and a second reference voltage to pass different operational amplifiers in different polarity control stage.

Gamma operational amplifier circuit, source driver and method for eliminating voltage offset

A digital-to-analog conversion apparatus and a current-mode interpolation buffer thereof are provided. The current-mode interpolation buffer comprises a current source, a first differential transistor pair, a second differential transistor pair and an output stage. The current source outputs a first current and draws a second current. Wherein, the amperages of the first current and the second current are dependent on a digital code. First differential transistor pair generates a first differential current according a first rough voltage, an analog voltage and the first current. Second differential transistor pair generates a second differential current according a second rough voltage, the analog voltage and the second current. Output stage generates the analog voltage according to the first differential current and the second differential current, where the analog voltage belongs to a rough range from the first rough voltage to the second rough voltage.

Digital-to-analog conversion apparatus and current-mode interpolation buffer thereof

A half-power buffer amplifier is disclosed. A buffer stage includes a first-half buffer stage and a second-half buffer stage, wherein an output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. The switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier. In one embodiment, the rail-to-rail differential amplifier and the buffer stage comprise half-power transistors operated within and powered by half of a full range spanning from power to ground.

Half-power buffer amplifier

An output buffer including a differential amplifier, a first and a second output stage, and a first and a second control stage is provided. The differential amplifier receives an input and a feedback signal and accordingly adjusts the level of the first and second control signals. The first control stage determines to provide a first current to an output terminal of the output buffer according to the level of the first and second control signals. The first control stage is biased under a high voltage and outputs one of the first control signal and the high voltage. The second control stage is biased under the low voltage and outputs one of the second control signal and the low voltage. The second output stage determines to provide a second current to the output terminal of the output buffer according to the signal generated by the first and second control stages.

Output buffer

A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage.

Driving circuit with slew-rate enhancement circuit

An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

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Tainan, Taiwan

Hung-Yu Huang