United Microelectronics Corp.

Hung-Yi Wu

Yi-Wen Chen

Chien-Ting Lin

Chun-Hsien Lin

Shih-Fang Tzou

Yuan-Chi Pai

Shao-Hua Hsu

Tong-Jyun Huang

En-Chiuan Liou

Ssu-I Fu

Yu-Ping Wang

Yu-Hsiang Lin

Chien-Ming Lai

Chi-Mao Hsu

Chien-Chung Huang

Cheng-Han Wu

Chih-Wei Yang

Jia-Rong Wu

Nien-Ting Ho

Shui-Yen Lu

Shih-Chieh Hsu

Che-Hua Hsu

Zhi-Cheng Lee

Yu-Ru Yang

Chia-Fu Hsu

Cheng-Guo Chen

Shin-Chi Chen

Ya-Huei Tsai

Chun-Chi Yu

Chi-Horn Pai

Jian-Cun Ke

Zen-Jay Tsai

Tsung-Yin Hsieh

Yu-Ting Tseng

Chang-Mao Wang

Hung-Ling Shih

Yu-Wei Cheng

Ying-Hung Chou

Yu-Feng Liu

Chih-Ho Wang

Shih-Hao Su

Yong-Fa Huang

Heng-Ching Huang

Kun-Sheng Yang

A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

Semiconductor device having metal gate structure

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Semiconductor device and method for fabricating the same

A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Semiconductor structure and manufacturing method of the same

A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Metal gate transistor

A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.

Photoresist removal method and patterning process utilizing the same

A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.

Semiconductor process

A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.

Method for forming photoresist patterns

A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate.

Removing method of a hard mask

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Keelung, Taiwan

Hung-Yi Wu