Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Yi Huang

Chih-Wei Chang

Chia-Hung Chu

Sung-Li Wang

Shuen-Shin Liang

Keng-Chu Lin

Min-Hsiu Hung

Ken-Yu Chang

Hsu-Kai Chang

Chien Chang

Chun-I Tsai

Chun-Hsien Huang

Kan-Ju Lin

Ching-Hwanq Su

Li-Wei Chu

Wei-Yip Loh

Po-Chin Chang

Yi-Hsiang Chao

Yu-Hsiang Liao

Ya-Huei Li

Lin-Yu Huang

Ming-Hsing Tsai

Yu-Ting Lin

Yu-Yun Peng

Mrunal Abhijith Khaderbad

Cheng-Wei Chang

Chih-wei Chang

Chun-Wen Nieh

Chun Chieh Wang

Pinyen Lin

Yuting Cheng

Tzu-Pei Chen

Harry Chien

Chi-Hung Chuang

Sheng-Tsung Wang

Hung-Hsu Chen

Yan-Ming Tsai

Chih-Shiun Chou

Tzu Pei Chen

Raghunath Putikam

Yi-Ning Tai

Kai-Yi Chu

Yen-Ming Chen

Chia-Hao Chang

Li-Zhen Yu

Dian-Hau Chen

Chien-Hao Chen

Shin-Yi Yang

Hsiang-Ku Shen

Chih-Tang Peng

Jr-Hung Li

Chih-Hao Wang

Chi-On Chui

De-Wei Yu

Ying-Liang Chuang

Shih-Wei Wang

Bo-Cyuan Lu

Tsung-Chieh Hsiao

Hong-Mao Lee

Yen-Chun Huang

Chun-Hung Liao

Cheng-Po Chau

Chia-Lin Chuang

Jin-Mu Yin

Chun-Cheng Chou

Kuan-Kan Hu

Kuan-Yu Yeh

Min-Hsuan Lu

Sung-li Wang

Chuan-Hui Shen

Shao-An Wang

TaiMin Chang

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

Semiconductor device including stacked via contact and method for manufacturing the same

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

Semiconductor device with conductive liners over silicide structures and method of making the semiconductor device

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Fin field-effect transistor device and method of forming the same

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Method and structure for barrier-less plug

A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

Gate to source drain interconnects

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Semiconductor structure and method of forming the same

In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.

Semiconductor devices and methods of manufacturing

Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Conductive feature formation and structure

Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Selective dual silicide formation

The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

Capping layer for liner-free conductive structures

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

Contact structure for semiconductor device

The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

Interconnect structure and manufacturing method for the same

Growing community of inventors

Hsin-Chu, Taiwan

Hung-Yi Huang