Faraday Technology Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Realtek Semiconductor Inc.

Unictron Technologies Corporation

Hung-Yi Chang

Yi-Hua Chang

Jeng-Huang Wu

Igor Elkanovich

Sheng-Hua Chen

Shih-Cheng Kao

Bi-Yang Li

Chih-Fu Chien

Chien-Hui Chuang

Kei-Kang Hung

Chun-Chang Liu

Sheng-Fan Yang

Chih-Shen Chou

Li-Ken Yeh

Tsung-Shou Yeh

Bing-Juo Chuang

Hsiang-Cheng Yang

Chun Ming Huang

Wei-Chieh Liao

Hao-Yu Tung

Jing-Chu Chan

Yi-Tzeng Lin

Wei-Chiao Wang

Yi-Hwa Chang

Chen-Kang Lin

Chung-Ling Liou

Yi-hwa Chang

A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes an input/output circuit, at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal transmitted through the input/output circuit and at least one test data signal transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to a voltage level of the at least one test result signal.

Semiconductor chip and sequence checking circuit

An interface device and a signal transceiving method thereof are provided. The interface device includes a slave circuit and a master circuit. The slave circuit is coupled to the master circuit and includes a first programmable delay line, a first output clock generator, and a first phase detector. The first programmable delay line provides a first adjusting delay amount according to a first adjust signal, and generates a first delayed clock signal by delaying a first clock signal according to the first adjusting delay amount. The first output clock generator generates a second clock signal according to the first delayed clock signal. The first phase detector detects a phase difference of the first clock signal and the second clock signal to generate first phase lead or lag information. The first adjust signal is generated according to the first phase lead or lag information.

Interface device and signal transceiving method thereof

An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.

An audio processing method includes the following operations. A calculated value is obtained according to multiple audio clock frequency information contained in multiple audio input packets. An audio sampling frequency is generated according to the calculated value and a link symbol clock signal. Multiple audio output packets corresponding to the audio input packets are generated according to the audio sampling frequency.

Audio processing device and audio processing method

An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer. The first trace layer is configured to receive a power. The bump layer is coupled to a die. The second trace layer and the third trace layer are coupled between the first trace layer and the bump layer, and include multiple ground traces and multiple power traces. The ground traces are located on both sides of at least one of the power traces, so that the ground traces isolate the at least one power trace and multiple signal traces. The power traces of the second trace layer are coupled to each other by a connecting power trace, and the ground traces of the third trace layer are coupled to each other by a connecting ground trace.

Interposer routing structure and semiconductor package

A communication interface structure for connection between dies is provided, including a memory die, processing dies and interconnection routings. The memory die includes a first interface edge, wherein the first interface edge is split into a plurality of interface groups. Each of the processing dies includes a second interface edge. Interconnection routings respectively connect the second interface edges of the processing dies to the interface groups of the memory die.

Communication interface structure between processing die and memory die

A signal receiving device adapting to a signal input mode and a signal processing method for the same are provided. The signal receiving device can determine various signal input modes, such as a differential signal or a single-ended signal, and select an appropriate signal source, such that the signal receiving device can not only receive the input signal correctly, but also adjust the received input signal to a differential signal with the same amplitude and opposite phases to make subsequent data analysis work easier.

Signal receiving device adapting to signal input mode and signal processing method for the same

An antenna device includes a circuit board and at least one chip antenna. The circuit board includes a clearance area and at least one signal feeding line disposed in the clearance area. The chip antenna includes a substrate and at least one resonance unit partially or wholly disposed on the surface of or within the substrate. The chip antenna is disposed in the clearance area of the circuit board and the resonance unit of the chip antenna is connected to the signal feeding line. A shortest distance from an edge of the clearance area to a nearest edge of the circuit board is greater than 1/10 of a smallest width of the circuit board. Therefore, the polarization direction of the chip antenna is approximately perpendicular to the upper surface of the circuit board, as well as the direction of the strongest signal strength of the radiation pattern is approximately parallel to the upper surface of the circuit board.

Antenna device capable of generating specific radiation pattern

An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving.

IO cell with multiple IO ports and related techniques for layout area saving

A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.

Power supply clamp circuit

An input/output buffer protection circuit, which comprises an I/O pad, an I/O buffer, an n-well control circuit, a gate control circuit, and a protection component. The I/O buffer includes a PMOS transistor and a NMOS transistor. The n-well control circuit is coupled to an n-well of the PMOS transistor. When an input voltage higher than a source voltage is applied, voltage at the n-well of the PMOS is increased by the n-well control circuit to the input voltage level. The gate control circuit is coupled to the gate terminal of the PMOS transistor and the input/output pad. When an input voltage higher than a source voltage is applied, voltage at the gate terminal of the PMOS is increased by the gate control circuit to the source voltage level. Wherein the gate control circuit comprises a transistor and the transistor transfers a high potential control voltage to the gate of the PMOS transistor in output mode. The protection component is coupled between the gate of the transistor and the I/O pad to generate a voltage drop down path and block the I/O pad signal from flowing back to the gate of the transistor.

Input/output buffer protection circuit

An input/output buffer. An input/output circuit has a transmission terminal coupled to an I/O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I/O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.

Input/output buffer

An input/output buffer. An input/output circuit is composed of a first PMOS transistor and a first NMOS transistor, has an I/O port coupled to an I/O pad, and a N-well region. An N-well control circuit controls the voltage level at the N-well region of the first PMOS transistor according to input signals at the I/O pad. A P-gate control circuit receives a second gate control signal and outputs to the gate of the first PMOS transistor. The P-gate control circuit is composed of a transmission gate and a third PMOS transistor. The transmission gate and the third PMOS transistor do not have to follow the design rule for ESD, and the wafer area required for the P-gate control circuit can be decreased because the P-gate control circuit is not directly connected to the I/O pad.

An electrostatic discharge protection circuit is connected to a bonding pad and a pre-stage driver. The electrostatic discharge protection circuit includes a PMOS transistor and a NMOS transistor and both connect in series. A source/drain region of the PMOS transistor is connected to a system power source, and the gate electrode is connected to a pre-stage drive, and the other source/drain region is connected to a source/drain region of the NMOS transistor, which is also connected to the bonding pad. Another source/drain region of the NMOS transistor is ground. The gate electrode of the NMOS transistor receives an output of the pre-stage driver. Another PMOS transistor is connected to a capacitor and is also connected to the source/drain region of a system power source and the gate electrode of the NMOS transistor.

Electrostatic discharge protection circuit

An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness. The voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.

Growing community of inventors

Hsinchu, Taiwan

Hung-Yi Chang