Industrial Technology Research Institute

Faraday Technology Corporation

National Yang Ming Chiao Tung University

Anpec Electronics Corporation

Hung-Wen Lu

Chau-Chin Su

Yeong-Jar Chang

Jen-Chien Hsu

Chih-Ning Chen

Chih-Heng Su

Hsueh-Chin Lin

Yen-Pin Tseng

Chien-Hsi Lee

Chia-Nan Wang

Uan-Jiun Liu

Shun-Min Chi

A driver circuit and a driving method with low inrush current are provided. The driving method includes steps of: supplying a charging current smaller than a high inrush current; outputting a pulse signal from a pulse generating circuit; enabling a light driving circuit to receive the charging current by the pulse signal and allowing the charging current to flow to an storage capacitor; turning on a switch component and a light-emitting assembly by the pulse signal; supplying an auxiliary current smaller than the high inrush current; enabling the light driving circuit to receive the auxiliary current and allowing auxiliary current to flow sequentially to the switch component and the light-emitting assembly; and emitting light by the light-emitting assembly with the discharging current of the storage capacitor and the auxiliary current of input power source.

Driver circuit and driving method with low inrush current

A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

Signal delay circuit

A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.

Built-in jitter measurement circuit

An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal.

Oscillator

Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one capacitor, coupled to the first switching module; a second switching module, coupled to the capacitor; a controllable reference voltage source, for providing a first reference voltage to charge/discharge the capacitor via the second switching module according to a control signal; a first comparator, coupled to the capacitor, for comparing a voltage drop on the capacitor and the first reference voltage to generate a first comparing result; and a control circuit, coupled to the controllable reference voltage source and the first comparator, for generating the control signal according to the comparing results.

Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit

In a precisely self-calibrating high-speed analog to digital converter the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.

Self-calibrating high-speed analog-to-digital converter

A system for clock and data recovery ('CDR') includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.

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Pingjhen, Taiwan

Hung-Wen Lu