TSMC Solid State Lighting Ltd.

International Business Machines Corporation

National Yang Ming Chiao Tung University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Lite-on Technology Corporation

Logitech Europe S.a.

Hung-Wen Huang

Ching-Hua Chiu

Hsing-Kuo Hsia

Hao-Chung Kuo

Yu Yu

Yun-Ting Hsu

Tien-Chang Lu

Jung-Tang Chu

Shing-Chung Wang

Yea-Chen Lee

Tsungwu Yu

Hung-Yi Kuo

Jui-Feng Kuan

Hung-Ming Chen

Chih-Kuang Yu

Hsien-Hsin Sean Lee

Sylvain Sauvage

Jasper Phua

Wei-Yi Hu

Tsun-Yu Yang

Chih-Ming Lai

Bengt Gunnar Brummer

Olivier Dumont

Po-Cheng Pan

Abhishek Patyal

A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Method for layout generation with constrained hypergraph partitioning

Input device with knob

A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.

Techniques for indicating and changing network communication settings of a computer host

A device includes a substrate; a group III-V semiconductor layer disposed over the substrate; and a seed layer disposed over the group III-V semiconductor layer. The substrate is a printed circuit board. The group III-V semiconductor layer includes a multiple quantum well (MQW) layer, a p-type doped layer, and an n-type doped layer. The seed layer includes a plurality of miniature elements. The miniature elements each contain a single-crystal material suitable for epitaxially growing the group III-V semiconductor layer. The miniature elements collectively cover less than 100% of a surface of the group III-V semiconductor layer.

Forming light-emitting diodes using seed particles

The present disclosure relates to methods for fabricating LEDs by patterning and etching an n-doped epitaxial layer to form regions of roughened surface of the n-doped layer and mesa structures adjacent to the roughened surface regions before depositing an active layer and the rest of the epitaxial layers on the mesa structures. The method includes growing epitaxial layers of an LED including an un-doped layer and an n-doped layer on a wafer of growth substrate. The method also includes patterning the n-doped layer to form a first region of the n-doped layer and a mesa region of the n-doped layer adjacent to the first region. The method further includes etching the first region of the n-doped layer to create a roughened surface. The method further includes growing additional epitaxial layers of the LED including an active layer and a p-doped layer on the mesa region of the n-doped layer.

Etching growth layers of light emitting devices to reduce leakage current

A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.

Method to remove sapphire substrate

A seed layer for growing a group III-V semiconductor structure is embedded in a dielectric material on a carrier substrate. After the group III-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group III-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure.

Provided is a method of fabricating a light-emitting diode (LED) device. The method includes providing a wafer. The wafer has light-emitting diode (LED) devices formed thereon. The method includes immersing the wafer into a polymer solution that has a surface tension lower than that of acetic acid. The polymer solution contains a liquid polymer and phosphor particles. The method includes lifting the wafer out of the polymer solution at a substantially constant speed. The method includes drying the wafer. The above processes form a conformal coating layer at least partially around the LED devices. The coating layer includes the phosphor particles. The coating layer also has a substantially uniform thickness.

Wafer level conformal coating for LED devices

A light-emitting device is capable of emitting a light having a wavelength ranging from 300 to 550 nm, and includes: a substrate; a p-type semiconductor layer disposed on the substrate; an active layer disposed on the p-type semiconductor layer; a n-type semiconductor layer disposed on the active layer and having a waveguide-disposing surface; and a waveguide structure formed on the waveguide-disposing surface of the n-type semiconductor layer and having a plurality of spaced apart nanorods extending from the waveguide-disposing surface.

Light-emitting device and method for making the same

Method for the light emitting diode (LED) having the nanorods-like structure is provided. The LED employs the nanorods are subsequently formed in a longitudinal direction by the etching method and the PEC method. In addition, the plurality of the nanorods is arranged in an array so that provide the LED having much greater brightness and higher light emission efficiency than the conventional LED.

Method for promoting light emission efficiency of LED using nanorods structure

Growing community of inventors

Hsinchu, Taiwan

Hung-Wen Huang