Qualcomm Incorporated

Hung Vuong

Robert Hardacker

Hyunsuk Shin

Santhosh Reddy Akavaram

Prakhar Srivastava

Rongtian Zhang

Ravi Kumar Sepuri

Manish Garg

Benish Babu

Chintalapati Bharath Sai Varma

Todd Christopher Reynolds

Satish Anand

Pratibind Kumar Jha

Sang Tran

Abhishek Ghosh

Baranidharan Muthukumaran

Shubham Kanwal

In some aspects, an apparatus includes a processing system that includes one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to send one or more memory access commands to a volatile memory. The one or more memory access commands are associated with a first address. The processing system if further configured to access, based on detecting a row-hammer condition associated with the one or more memory access commands, a physically adjacent row mapping table to determine at least a second address. The first address and the second address correspond to physically adjacent rows within the volatile memory. The processing system if further configured to send one or more row refresh commands to the volatile memory based on the row-hammer condition. The one or more row refresh commands are associated with at least the second address.

Row-hammer condition mitigation using a physically adjacent row mapping table

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

Host management of flash memory with shared write buffer

A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

Host device caching of flash memory address mappings

Data may be purged from a memory device in a manner confined to a particular partition of a memory device having two or more partitions. Logical memory blocks may be de-mapped from physical memory blocks of a first storage partition of the memory device. De-mapped physical memory blocks of the first storage partition may be listed in a local de-mapped block list uniquely associated with the first storage partition. A local purge command may be received from a host device. In response to the local purge command, at least a portion of the de-mapped physical memory blocks listed only in the local de-mapped block list are purged.

Flash memory local purge

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Hung Vuong