Silicon Integrated Systems Corporation

Hung-Ta Pai

Hung-Ming Lin

Hung-Ju Huang

Chen-Yi Lee

Ming-Hao Liao

Chien-Hsiu Huang

Chun-An Tu

Lin-Tien Mei

Cheng-Hsien Chen

A TV decoder. The decoder comprises a converter producing a plurality of first bits by sampling a base-band TV signal within a sampling period, and transmitting the first bits in groups, wherein the first bits in each one of the groups undergo parallel transmission through a plurality of first signals, and a demodulator receives the first bits and produces a plurality of second bits controlling the first signals, wherein the second bits are sequentially transmitted through a second signal input to the converter.

TV decoder

A method is adapted for compressing an image data block, and includes the steps of:

Adaptive quantization using code length in image compression

A signal transmission device adapted to transmit an n-bit parallel digital signal is used for avoiding a transmission error. The device includes a detector for receiving a first and a second n-bit digital data consecutively occurred in the n-bit parallel digital signal, proceeding a first calculation to obtain a changed value, and outputting an indicating signal while the changed value is larger than a threshold, an encoder electrically connected to the detector for receiving the indicating signal and the second n-bit digital data, proceeding a second calculation, and outputting an encoded second n-bit digital data to reduce the changed value between the first n-bit digital data and the encoded second n-bit digital data below the threshold, and a decoder electrically connected to the detector and the encoder receiving the indicating signal and the encoded second n-bit digital data, proceeding a third calculation, and recovering the second n-bit digital data.

Signal transmission device and method for avoiding transmission error

An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Apparatus and method for automatic determination of operating frequency with built-in self-test

The present invention discloses an apparatus and method for cache memory connection of texture mapping, applied in a computer graphic processing system by storing image texels in cache memories. The apparatus comprises a plurality of cache memories. An array of image texels are stored in a plurality of cache memories to reduce the area occupied by cache memories of the computer graphic processing system. Besides, the apparatus and method of the present invention can be applied in the well-known mapping methods: selecting the nearest point, bilinear filtering and trilinear filtering. A plurality of multiplexers are used to reorganize the plurality of cache memories so as to increase the utilization efficiency of the apparatus of the present invention.

Apparatus and method for cache memory connection of texture mapping

A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Digital clock throttling means

An apparatus of reducing power consumption of a single-ended Static Random Access Memory (hereinafter referred as SRAM) is provided. The apparatus consists of at least an extra column of status memory cell and a majority detector by which a bit status of a written data is detected and by which the value of the bit status is written into the extra column of status memory cell. The apparatus further includes a data scrambler by which the written data is converted into a storage data with a minority of 0 bits based on the value of bit status and by which the storage data is written into the main single-ended SRAM cell. The apparatus further includes a data de-scrambler by which the storage data in the main single-ended SRAM cell is converted into its original format based on the value of bit status stored in the extra column of memory cell and by which the data in its original format is output. Since the data stored in the main single-ended SRAM cell has a majority of 1 bits, the apparatus can reduce the power consumption of the single-ended SRAM.

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Taichung Hsien, Taiwan

Hung-Ta Pai