Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Shu Huang

Ming Chyi Liu

Ming-Chyi Liu

Tung-He Chou

Chien-Chih Chou

Yu-Chang Jong

Jhih-Bin Chen

Jhu-Min Song

Yu-Lun Lu

Tsung-chieh Tsai

Yi-Kai Ciou

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

Semiconductor device having a gate electrode with a top peripheral portion and a top central portion, and the top peripheral portion is a protrusion or a depression surrounding the top central portion

A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Semiconductor structure and forming method thereof

In some embodiments, the present disclosure relates to an image sensor, including a semiconductor substrate, a plurality of photodiodes disposed within the semiconductor substrate, and a deep trench isolation structure separating the plurality of photodiodes from one another and defining a plurality of pixel regions corresponding to the plurality of photodiodes. The plurality of pixel regions includes a first pixel region sensitive to a first region of a light spectrum, a second pixel region sensitive to a second region of the light spectrum, and a third pixel region sensitive to a third region of the light spectrum. The first pixel region is smaller than the second pixel region or the third pixel region.

Unequal CMOS image sensor pixel size to boost quantum efficiency

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

Passivation structure with increased thickness for metal pads

The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.

Flash memory structure with enhanced floating gate

Device with a recessed gate electrode that has high thickness uniformity

A method of manufacturing a semiconductor device includes: forming a conductive pad region over a substrate; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first area of the conductive pad region; and removing portions of the second passivation layer to expose a second area of the conductive pad region.

Pad structure and manufacturing method thereof in semiconductor device

A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.

Double channel memory device

The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

A semiconductor device includes a substrate, a conductive pad region electrically coupled to the substrate, a first dielectric layer over the conductive pad region, and a passivation layer over the first dielectric layer, wherein the passivation layer includes a laterally-extending portion covering the first dielectric layer and a vertically-extending portion on a sidewall of the first dielectric layer. The laterally-extending portion and the vertically-extending portion of the passivation layer are joined along a vertically-extending boundary.

In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

A method of manufacturing a semiconductor device includes: forming a memory cell on a substrate; forming a conductive pad region to electrically couple to the memory cell; depositing a dielectric layer over the conductive pad region; forming a first passivation layer over the dielectric layer; etching the first passivation layer through the dielectric layer, thereby exposing a first area of the conductive pad region; forming a second passivation layer over the first passivation layer and the exposed first area of the conductive pad region; and etching the second passivation layer to expose a second area of the conductive pad region.

Growing community of inventors

Taichung, Taiwan

Hung-Shu Huang