Advanced Micro Devices Corporation

National Semiconductor Corporation

Aplus Flash Technology, Inc.

Actel Corporation, Inc.

Other

Fujitsu Corporation

Fujitsu Amd Semiconductor Limited

Hung-Sheng Chen

Peter Wung Lee

Yu Nan Sun

Vei-Han Chan

Angela Tai Hui

Mark S Chang

Chih Sieh Teng

Chi K Chang

Unsoon Kim

Tatsuya Kajita

Fu-Chang Hsu

Hsing-Ya Tsao

Fei Wang

Mark T Ramsbey

John L McCollum

Mark W Randolph

Yue-Song He

Kashmir S Sahota

Frank W Hawley

Yowjuang William Liu

Richard J Huang

Chin-Miin Shyu

Huan-Chung Tseng

C S Teng

Larry Moberly

Tim Nguyen

Chang-Kai Huang

A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Non-volatile programmable memory cell for programmable logic array

In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Array architecture and process flow of nonvolatile memory devices for mass storage applications

The present invention comprises an antifuse having a hemispherical grained (HSG) layer and a method of forming antifuse having a hemispherical grained (HSG) layer. The antifuse of the present invention comprises a plurality of layers, the first being a lower electrode that is disposed on an impurity region in a semiconductor substrate. A dielectric layer is disposed on the lower electrode, wherein the dielectric layer has a planar surface. A non-conductive hemispherical grain (HSG) layer is formed on the planar surface of the dielectric layer and an upper electrode is disposed on said non-conductive hemispherical grain (HSG) layer forming the antifuse.

Antifuse structure and a method of forming an antifuse structure

A method for making a self-aligned isolated memory core for a flash memory wafer includes the steps of establishing control gates for memory cells in the core by depositing a first polysilicon layer on a silicon substrate, etching the first layer, and depositing a second polysilicon layer on the substrate, with the polysilicon layers being separated by an interpoly dielectric layer. Then, after the control gates have been established, isolation trenches are formed in the silicon substrate between regions by self-aligned etching processes.

Method for forming isolation in flash memory wafer

In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration

In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.

Stacked gate flash memory cell with reduced disturb conditions

A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

Method for producing a shallow trench isolation filled with thermal oxide

A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

Process for fabricating an integrated circuit with a self-aligned contact

A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

Breakdown-free high voltage input circuitry

Shallow trench isolation filled with thermal oxide

In the present invention a flash memory configuration is disclosed that eliminates the need for one of two pump circuits that are commonly required to support an erase function of memory cells on a flash memory chip. The flash memory cells are placed into a triple well structure with a P-well contained within a deep N-well that resides on a P-substrate. The bias voltages for erase of the flash memory cells are chosen so as to require only one voltage pump circuit to be included in the flash memory chip. The chip bias, V.sub.DD, is used for the source of the memory cells and a negative gate voltage is raised in magnitude to maintain the efficiency of the erase operation. The P-well is biased with a negative voltage that is sufficient to prevent the high negative voltage connected to the gate from causing breakdown in word line decoder circuits. The deep N-well and the P-substrate are biased such as to back bias the P/N junctions between the triple well structure.

Erase condition for flash memory

An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.

Scalable and reliable integrated circuit inter-level dielectric

A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.

Growing community of inventors

San Jose, CA, United States of America

Hung-Sheng Chen