Silicon Storage Technology, Inc.

Hung Quoc Nguyen

Hieu Van Tran

Anh Ly

Thuan Vu

Sang Thanh Nguyen

Loc Bao Hoang

Vishal Sarin

Nasrin Jaffari

Steve Choi

Nhan Do

Sheng-Hsiung Hsueh

Wingfu AAron Lau

Alexander Kotov

Isao Nojima

Mark Reiten

William Saiki

Yuniarto Widjaja

Vipin Tiwari

Bomy A Chen

Amitay Levi

Tam Minh Nguyen

Tho Ngoc Dang

Elbert Lin

Viet Tan Nguyen

Dana Lee

Xian Liu

Feng Zhou

Ya-Fen Lin

Viktor Markov

Zhixian Chen

Pavel Klinger

Nianglamching Hangzo

Hung Thanh Nguyen

Jong-Won Yoo

Thuc Tran Bui

Wang Xinpeng

Guo-Qiang Lo

A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Virtual ground non-volatile memory array

An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

Programming circuit and method for flash memory array

An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Dynamic programming of advanced nanometer flash memory

A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

Three-dimensional flash NOR memory system with configurable pins

During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

Flash memory system using negative high voltage level shifter

The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.

Sensing amplifier comprising fully depleted silicon-on-insulator transistors for reading a selected flash memory cell in an array of flash memory cells

Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

High speed sensing for advanced nanometer flash memory device

A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.

Power sequencing for embedded flash memory devices

A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

Flash memory system using complementary voltage supplies

A circuit and method are disclosed for operating a non-volatile memory device, comprising time sampling a reference current or voltage in a floating holding node to obtain a hold voltage and applying the hold voltage in sensing circuitry.

Sensing circuit with sampled reference current or voltage for flash memory system

Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.

Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system

The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.

Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems

A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

Growing community of inventors

Fremont, CA, United States of America

Hung Quoc Nguyen