International Business Machines Corporation

Globalfoundries Inc.

Hung Qui Le

Dung Q Nguyen

Brian William Thompto

Hoichi Cheong

Jose Eduardo Moreira

Susan Elizabeth Eisen

Jentje Leenstra

Sundeep Chadha

David Allen Hrusecky

Albert James Van Norstrand, Jr

Robert Allen Cordes

James Allan Kahle

Lee Evan Eisen

Christopher Michael Abernathy

Bruce Joseph Ronchetti

Balaram Sinharoy

Richard James Eickemeyer

Steven Wayne White

David R Terry

Mary Douglass Brown

John Stephen Muhich

Michael Joseph Genden

Steven J Battle

Cathy May

Paul Joseph Jordan

Bradly George Frey

David James Shippy

James Wilson Bishop

Harold Wade Cain, Iii

Bryan J Lloyd

Elizabeth A McGlone

Kenneth Lundy Ward

Larry Edward Thatcher

Brian R Konigsburg

Joshua W Bowman

Maureen Anne Delaney

Cliff Kucharski

John Barry Griswell, Jr

William John Starke

Brian David Barrick

Markus Kaltenbach

Maarten Jakob Boersma

Alexander Erik Mericas

Shih-Hsiung Stephen Tung

Francis Patrick O'Connell

Salma Ayub

Giles R Frazier

David S Levitan

Kevin Franklin Reick

Scott Barnett Swaney

William Elton Burky

Jose Angel Paredes

Robert J Blainey

Edward John Silha

Sam Gat-Shang Chu

Andreas Wagner

Guy L Guthrie

Derek E Williams

Jeffrey A Stuecheli

Charles Ray Johns

Pradip Bose

Hubertus Franke

Silvia Melitta Mueller

Michael Stephen Floyd

David Arnold Luick

Ravi Nair

Peter Juergen Klim

Pratap Chandra Pattnaik

Sheldon Bernard Levenstein

Ronald P Hall

Raul Esteban Silvera

Kurt Alan Feiste

David Scott Ray

Charles Roberts Moore

Jeffrey Carl Brownscheidle

Kimberly Marie Fernsler

Alper Buyuktosunoglu

Anthony Saporito

Philip George Emma

Maged M Michael

Naresh Nayar

Randal Craig Swanberg

Phillip G Williams

Kattamuri Ekanadham

Christian Zoellin

Brian William Curran

Peichun Peter Liu

Soummya Mallick

Thomas James Heller, Jr

Vikas Agarwal

Donald George Mikan, Jr

Miles Robert Dooley

Steven R Kunkel

Michael Kevin Ciraula

David Andrew Schroter

Erdem Hokenek

Michael Klaus Kroener

Todd Alan Venton

Benjamin Herrenschmidt

Larry Scott Leitner

An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.

Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Instruction handling for accumulation of register results in a microprocessor

A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.

Instruction streaming using state migration

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Dynamic update of the number of architected registers assigned to software threads using spill counts

A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.

Thread transition management

Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.

Multiple streams execution for hard-to-predict branches in a microprocessor

A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.

Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry

Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Independent mapping of threads

A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number 'N' of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Check pointing of accumulator register results in a microprocessor

Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.

Extended prefix including routing bit for extended instruction format

A system and/or method for processing information is disclosed that has at least one processor; a register file associated with the processor, the register file sliced into a plurality of STF blocks having a plurality of STF entries, and in an embodiment, each STF block is further partitioned into a plurality of sub-blocks, each sub-block having a different portion of the plurality of STF entries; and a plurality of execution units configured to read data from and write data to the register file, where the plurality of execution units are arranged in one or more execution slices. In one or more embodiments, the system is configured so that each execution slice has a plurality of STF blocks, and alternatively or additionally, each of the plurality of execution units in a single execution slice is assigned to write to one, and preferably only one, of the plurality of STF blocks.

Slice-target register file for microprocessor

A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.

Decoupling of conditional branches

Growing community of inventors

Austin, TX, United States of America

Hung Qui Le