Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.P.

Compaq Information Technologies Group, L.p.

Other

Hewlett Packard Enterprise Development LP

Hung Q Le

David F Heinrich

David J Delisle

Theodore F Emerson

Patrick R Cooper

David J Maguire

Maria L Melo

Sompong Paul Olarig

Michael F Angelo

Paul R Culley

Charles J Stancil

Randall L Hess

Robert L Noonan

Paul B Rawlins

Henry F Lada, Jr

Gaines C Teague

Dean P Perkins

James H Garrett

Richard O Waldorf

Daniel B Reents

John M Gromala

A method for initializing a memory subsystem () of a management controller () includes, with an additional memory initialization module () of the management controller (), initializing the memory subsystem () of the management controller () in response to the memory subsystem () not being properly initialized. A management controller () includes a memory subsystem () including a memory controller () and a memory (); firmware () able to initialize the memory subsystem (); and a memory initialization module () to initialize the memory subsystem () if the memory subsystem () is not properly initialized.

Initializing a memory subsystem of a management controller

A memory controller containing one or more ports coupled to a buffer selection logic and a plurality of buffers. Each buffer is configured to store write data associated with a write request and each buffer is also coupled to the buffer selection logic. The buffer selection logic is configured to store write data associated with a write request from at least one of the ports in any of the buffers based on a priority of the buffers for each one of the ports.

Storing data in any of a plurality of buffers in a memory controller

A system comprising a memory subsystem having at least one memory device, and a memory controller to control access of the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first portion of the memory subsystem, and to store data without ECC information in a second portion of the memory subsystem.

Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information

A system supports allocating buffer storage for multiple buffers from a common storage area and dynamically reconfiguring the common storage area to shift buffer storage between buffers. A buffer mechanism controls access to buffer storage allocated within the common storage area. An allocation mechanism changes buffer storage allocation by moving one or more boundary pointers after verification that the reconfiguration is valid. The system provides more efficient use of memory and can allow a smaller memory requirement than conventional systems with fixed buffer storage sizes.

Dynamically adaptive buffer mechanism

A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared. If an ISA read or write cycle is destined for a secured peripheral device denoted by its shadowed status within the shadowing registers, then securing of that device is achieved regardless of where that device is plugged into a corresponding socket location. In this manner, securable device identification numbers and base addresses can be kept track of (shadowed) such that the shadowing information will purposely mask accesses to relocated ISA Plug and Play secured devices and/or slots.

Apparatus and method for maintaining secured access to relocated plug and play peripheral devices

A computer system, bus interface unit, and method are provided for securing certain devices connected to an I C bus. Those devices include any device which contains sensitive information or passwords. For example, a device controlled by a I C-connected device bay controller may contain sensitive files, data, and information to which improper access may be denied by securing the device bay controller. Moreover, improper accesses to passwords contained in non-volatile memory connected to the I C bus must also be prevented. A bus interface unit coupled within the computer contains registers, and logic which compares the incoming I C target and word addresses with coded bits within fields of those registers. If the target or word address is to a protected address or range of addresses, then an unlock signal must be issued before the security control logic will allow the target or word address to access the I C bus or addressed device thereon. The unlock signal can be assigned to a particular slot among numerous slots, wherein the slots are arranged in hierarchical order. This allows a system administrator the capability to unlock accesses to protected non-volatile memory, and thereby allowing the system administrator to change passwords within one portion of non-volatile memory, and possibly allowing a lower priority user to access and change a password within another portion of non-volatile memory. The slot which accommodates an unlock signal assigned to the system administrator is altogether separate from a slot assigned to a non-system administrator or user.

Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus

A computer system, bus interface unit, and method is provided for programmably modifying securable resources of the computer. Those resources may be devices which can be coupled to peripheral buses of the computer, or which may contain or allow access to sensitive information that must be secured against improper access. The security system thereby functions to block accesses to certain devices based on the status of the user seeking access. Passwords stored in the security system are matched against locally and distally entered passwords from either the user of that particular computer system, an administrator of a subset of localized computer systems, or a system administrator in charge of all networked computer systems. The present security system is thereby hierarchical in nature and can be programmed by the system administrator such that the assignment of unlocked signals arising from password comparisons can be programmably mapped to various securable devices. In this fashion, a user can gain access to certain resources at one time and then later, based on the system administrator re-programming a slot assignment register, the user may no longer be given access to that device. The system administrator can therefore impart flexibility to device security mechanisms that exist within personal computers.

Apparatus and method for programmably and flexibly assigning passwords to unlock devices of a computer system intended to remain secure

A computer system according to the present invention implements a self-modifying &ldquo;fail-safe&rdquo; password system that allows a manufacturer or site administrator to securely supply a single-use password to users who lose a power-up password. The fail-safe password system utilizes at least one fail-safe counter, an encryption/decryption algorithm, a public key, and a secure non-volatile memory space. The fail-safe password is derived by generating a hash code using SHA, MD5,or a similar algorithm and encrypting the result. The fail-safe password is then communicated to the user. After the user enters the fail-safe password, the computer system generates an internal hash value and compares it with the hash code of the decrypted fail-safe password. When the decrypted fail-safe password matches the internal hash value, the user is allowed access to the computer system.

Computer access via a single-use password

A clock generation circuit is provided within an electronic computer system to adjust the phase of a clocking signal provided to various subsystems of the electronic system. A first phase-locked loop (PLL) is provided to establish multiple phases of a first reference clock. One of those phases is selected as a second reference clock, and a second PLL synchronizes the clocking signal to that second reference clock. Each subsystem and associated load which receives the clocking signal has a corresponding clock generation circuit comprising the second PLL. The second PLL for one subsystem can adjust the clocking signal phase prior to that subsystem receiving the clocking signal. The amount by which the second PLL adjusts phase on clocking signal may be different than that by which another, second PLL adjusts the clocking signal arriving on another subsystem. In all instances, however, the clocking signal arriving at the various subsystems are independently and variably changed to match the unique load characteristics of each subsystem using feedback of the clocking signal to the input of each respective second PLL.

Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew

A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array. The setting of the remap bit enables the remapper to deflect accesses to the flash ROM. The restarting of the clock signal to the microcontroller to switch the ownership of the flash ROM back to the microcontroller. In the event that the microprocessor needs to regain access to the flash ROM contents, the microprocessor writes to the mailbox register of the arbiter to request access to the flash ROM. The microprocessor waits for a confirmation from the arbiter that the microcontroller is entering an idled mode. Next, the microprocessor halts the clock of the microcontroller. These events cause the microcontroller to float or tristate the signal lines going from the microcontroller to the flash ROM such that the microprocessor can drive the signal lines without any conflict potentials. In this manner, the microprocessor can still access the shared flash ROM after it has booted up. Thus, the system cost is reduced, the system reliability is enhanced, while the system accessibility to the flash ROM after the boot-up period is still preserved.

Flash ROM sharing between processor and microcontroller during booting

The present invention relates to a low latency serial bus system for shadowing registers between first and second digital devices. Either the first device or the second device may initiate a data transfer cycle on the serial bus when data in a shadowed register of that device has changed. The data transfer cycle includes a first frame where data is transferred from the first device to the second device and a second frame where data is transferred from the second device to the first device. The devices do not initiate a subsequent data transfer cycle for changed data if the changed data can be transferred in the current data transfer cycle.

Serial bus system for shadowing registers

A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.

Programmable memory device that supports multiple operational modes

In accordance with the invention, a computer system is provided with a flash read-only-memory (ROM), a microcontroller and a data port. The microcontroller initially owns the flash ROM. The microcontroller further has a separate ROM upon which it can execute boot-up instructions. After booting up, the microcontroller checks the flash ROM contents, preferably by performing a check-sum of the flash ROM contents. If the checksum of the flash ROM contents matches an expected value, the microcontroller releases ownership of the flash ROM to the computer system so that the computer system boots-up as normal. If the microcontroller determines that the flash ROM has become corrupted, the microcontroller accesses the data port and looks for a flash programming protocol. If the protocol is present at the data port, the microcontroller receives the data from the data port and programs the flash ROM accordingly. In this manner, the flash ROM can be updated to a good known state, even if the computer system is not able to boot up due to, among other things, the corruption of the flash ROM.

Growing community of inventors

Katy, TX, United States of America

Hung Q Le