Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Pin Ko

Alexander Kalnitsky

Wei Cheng Wu

Shih-Hao Lo

Wei-Cheng Wu

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a gate dielectric structure on a substrate. A sidewall spacer is formed around the gate dielectric structure. A metal structure is formed over the gate dielectric structure. A gate body layer is formed over the metal structure. A lower portion of the gate body layer is cupped by the metal structure. A top surface of the gate body layer is vertically offset from a top surface of the metal structure. A conductive via is formed over the metal structure. The conductive via is disposed between outer sidewalls of the gate body layer.

Method of forming a gate structure in high-κ metal gate technology

Various embodiments of the present disclosure are directed towards a semiconductor device including a gate structure. The semiconductor device further includes a pair of spacer segments on a semiconductor substrate. A high-&#x3ba; gate dielectric structure overlies the semiconductor substrate. The high-&#x3ba; gate dielectric structure is laterally between and borders the spacer segments. The gate structure overlies the high-k gate dielectric structure and has a top surface about even with a top surface of the spacer segments. The gate structure includes a metal structure and a gate body layer. The gate body layer has a top surface that is vertically offset from a top surface of the metal structure and further has a lower portion cupped by the metal structure.

Gate structure in high-&#x3ba; metal gate technology

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a first FET, and a second FET formed over the substrate. The substrate has a first surface and a second surface, and the first surface and the second surface form a step. The first FET comprises a first gate dielectric layer over the first surface of the substrate. The second FET comprises a second gate dielectric layer thinner than the first gate dielectric layer over the second surface of the substrate.

Growing community of inventors

Hsin-Chu, Taiwan

Hung-Pin Ko