Texas Instruments Corporation

Hung Ong

Abhijeet Ashok Chachad

David Matthew Thompson

Bipin Prasad Heremagalur Ramaprasad

Ramakrishnan Venkatasubramanian

Oluleye Olorode

Sanjive Agarwala

Quang-Dieu An

Kyle Castille

An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Prefetch management in a hierarchical cache system

This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

Zero latency prefetching in caches

A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Prefetch kill and revival in an instruction cache

A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it's cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.

Using L1 cache as re-order buffer

An embodiment of the invention provides a method for decreasing power in an L1 program memory of a multi-level memory system. The power is decreased by enabling a sleep mode in the L1 program memory. The sleep mode determines when the L1 program memory will not be accessed for a period of time. When it is determined that the L1 program memory will not be accessed for a period of time, the voltage applied to the memory array is reduced. When it is determined that the L1 program memory will be accessed, the voltage applied to the memory array is increased.

Reducing current leakage in L1 program memory

The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

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Plano, TX, United States of America

Hung Ong