Adeia Semiconductor Bonding Technologies Inc.

Sunpower Corporation

Novellus Systems Incorporated

Maxeon Solar Pte. Ltd.

Neoconix, Inc

Hung-Ming Wang

David Noel Light

David R Baker

Bulent Mehmet Basol

Homayoun Talieh

Paul Loscutoff

Mark A Kleshock

Cyprian Emeka Uzoh

John W Smith

Seung Bum Rim

Lewis C Abra

David C Okawa

Raphael M Manalo

Mohamad Ridzwan Mustafa

Neil G Bergstrom

Thomas H DiStefano

David D Smith

Masud Beroz

Delin Li

Sung Dug Kim

Joseph Frederick Behnke

Michael Warner

Matthew J Dawson

Arnold Villamor Castillo

John A Grange

David Rodney Baker

Peter Tho Nguyen

Dennis Castillo

Dexter Shih-Wei Pao

Arnold V Castillo

A wafer plating fixture for use in simultaneously electroplating a two substrates. The wafer plating fixture including: an electrically conductive carrier bus; a plurality of contact clips electrically coupled to the carrier bus and configured to hold the two substrates in place and electrically couple the two substrates to the carrier bus; and a non-conductive substrate backer to separate the two substrates coupled to the carrier bus. A method of electroplating a plurality of substrates. The method including: mounting two substrates to be plated onto a wafer plating fixture; mounting the wafer plating fixture on a continuous belt of plating system; dipping the wafer plating fixture with the two substrates held thereon into an electroplating bath; and applying a voltage to the two substrates via the wafer plating fixture.

Dual wafer plating fixture for a continuous plating line

Methods of fabricating solar cells having a plurality of sub-cells coupled by cell level interconnection, and the resulting solar cells, are described herein. In an example, a solar cell includes a plurality of sub-cells. Each of the plurality of sub-cells includes a singulated and physically separated semiconductor substrate portion. Each of the plurality of sub-cells includes an on-sub-cell metallization structure interconnecting emitter regions of the sub-cell. An inter-sub-cell metallization structure couples adjacent ones of the plurality of sub-cells. The inter-sub-cell metallization structure is different in composition from the on-sub-cell metallization structure.

Solar cell having a plurality of sub-cells coupled by cell level interconnection

A solar cell and a solar laminate are described. The solar cell can have a front side which faces the sun during normal operation and a back side opposite front side. The solar cell can include conductive contacts having substantially reflective outer regions disposed on the back side of the solar cell. The solar laminate can include a first encapsulant, the first encapsulant disposed on the back side of the solar cell and a second encapsulant. The solar laminate can include the solar cell laminated between the first and second encapsulant. The substantially reflective outer regions of the conductive contacts and the first encapsulant can be configured to scatter and/or diffuse light at the back side of the solar laminate for substantial light collection at the back side of the solar cell. Methods of fabricating the solar cell are also described herein.

Bifacial solar cells with reflective back contacts

Solar cells are attached together to form a plating assembly. The plating assembly is attached to a belt, which transports the plating assembly through a plating chamber where metal is electroplated on the solar cells. The electroplated metal is patterned to form metal contact fingers. After the metal is electroplated, the plating assembly is singulated to separate the two solar cells.

Structures and methods for forming electrodes of solar cells

Disclosed is an electrical connector having a substrate and movable electrical contacts which are mounted to the substrate and extend a distance D from the substrate. A layer of compressible material (such as a foam or elastomeric material) is positioned on the substrate adjacent at least some of the electrical contacts and ideally has an uncompressed thickness slightly greater than the distance D to provide for protection of the electrical contacts. When a mating electrical device such as an electrical connector or other circuit member is mated to the electrical connector with its electrical contacts and its layer of compressible material, the layer of compressible material is compressed to a thickness less than the distance D, allowing the contacts to make a suitable electrical interconnection to the mating electrical device. The compressible material may be selected which has a force-to-compression plot which includes at least one inflection, defining a first region on one side of the inflection where a given increment of force provides a larger increment of compression and a second region on the other side of the inflection where the same increment of compressive force provides a substantially smaller increment of compression. The compressible material can function to prevent damage to the movable electrical contacts from handling, packing, shipping, assembly, testing, connection and/or mating of the connector.

Electrical connector with electrical contacts protected by a layer of compressible material and method of making it

A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.

Method of forming contact layers on substrates

Consistent excess conductive material is provided for plated conductors in integrated circuit metallization, regardless of the size and depth of trenches/vias into which the conductive material is deposited. Accordingly, subsequent processing (e.g., material removal) can be consistent and efficient for wafers with different feature sizes (particularly different depths), and for wafers at different metallization levels.

Efficient wafer processing technology

A method is disclosed for making a microelectronic package. A material is applied to a first major surface of a microelectronic element to reduce the heights of protrusions projecting from the first major surface. The microelectronic element is assembled to a microelectronic component. A method of forming protrusions and an assembly incorporating the microelectronic element having protrusions is also disclosed.

Microelectronic assemblies having low profile connections

Flexible leads for making electrical connection in microelectronic components includes two metallic layers. The structural or core layer of the lead is formed having a hardness greater than the hardness of the second layer. The relative hardness between the first and second layers is achieved by controlling the grain size during deposition of the respective layers from an electroless or electroplating bath.

Graded metallic leads for connection to microelectronic elements

A layered lead is disclosed including a layer of structural material which has top and bottom sides, a layer of fatigue-resistant material on the top and bottom surfaces and a layer of bonding material covering the fatigue-resistant layer on the bottom surface for connection to a contact on a chip. An asymmetrical distribution of bonding material on the top and bottom sides may be used to provide reinforcement of the lead against stress. The fatigue-resistant material also acts as a barrier against diffusion between the metal layers.

Layered lead structures

Metal leads are formed on a copper conductive layer by applying a first resist and a main resist over the first resist, and forming aligned openings in these resist. A bottom layer of cover metal such as gold is plated onto the copper conductive layer in these openings, followed by a principal metal such as copper. The main resist is then removed so as to expose edges of the principal metal layer. A jacket of cover metal is plated onto the exposed edges and surfaces of the principal metal layer. During this stage, the first resist prevents deposition of the cover metal except on the leads. The jacket merges with the bottom layer of cover material, so as to form a continuous coating extending around the perimeters of the leads. The first resist is removed, and the conductive layer is etched away. The cover metal protects the principal metal during the etching stage.

Metal-jacketed lead manufacturing process using resist layers

Growing community of inventors

San Jose, CA, United States of America

Hung-Ming Wang