Taiwan Semiconductor Manufacturing Comp. Ltd.

Synopsys, Inc.

National Yang Ming Chiao Tung University

Synopsys Taiwan Co., Ltd.

Evermore Technology Inc.

Rdc Semiconductor Co., Ltd.

Hung-Ming Chen

Tsung-Lin Lee

Feng Yuan

Chang-Yun Chang

Chih Chieh Yeh

Yee-Chia Yeo

Hung-Li Chiang

Cheng-Yi Peng

Chih-Sheng Chang

Chu-Yun Fu

Hung-Ta Lin

Shin-Yeh Huang

Shu-Tine Yang

Chih-Hao Chang

Chih-Hao Yu

Clement Hsingjen Wann

Fu-Liang Yang

Chien-Chao Huang

Tung-Chieh Chen

Chun-Sheng Liang

Chih-Chieh Yeh

Yu-Chang Lin

Chih-Pin Tsao

Jen-Hsiang Lu

Chung-Ting Li

Hou-Ju Li

Yuan-Sheng Chen

Wu-Hsiung Huang

Tsu-Pin Weng

Jia-You Jiang

Po-Cheng Pan

Yi-Peng Weng

Shao-Ming Yu

Jui-Feng Kuan

Kuan-Neng Chen

Hsien-Hsin Sean Lee

Su-Yu Yeh

Wei-Yi Hu

Ko-Bin Kao

Chun-Yu Chen

Li-Jen Wu

Tsun-Yu Yang

Hung-Wen Huang

Chia-Hung Chung

Yong-Ting Wu

Ming-Fang Lai

Yin-Shen Chu

Wen-Hsing Kuo

Wen-Chieh Hsieh

Abhishek Patyal

Ching-Yu Chin

An-Nan Tan

Ren-Jie Lee

Ying-An Shih

Yi-Yuan Ho

The present invention relates to an authentication information manager computer program product, which is executed by a processing unit. The computer program product includes: a physical private key acquisition module configured to receive an identity information to form an initialization authentication information including a part of the identity information; an authentication information management module configured to record a first set of authentication information for logging into a first networking application; and a multiparty multifactor dynamic strong encryption authentication transmission module configured to implement a multiparty multifactor dynamic digital authentication method with strong encryption to transmit the transfigurated initialization authentication information to a network application serving device including an authentication information manager back end and a third-party security serving equipment to be verified.

Authentication information manager computer program product and device

The present invention relates to a cyber security authentication method for a displayless networking device. The method includes randomly generating an ephemeral decryption key in a displayless networking device application server; providing the ephemeral decryption key and a network address of the displayless networking device to a user device via an optical identifier; initiating a multi-party multi-factor dynamic strong encryption authentication scheme in the user device based on the ephemeral decryption key and the network address to obtain an ephemeral credential; and authenticating an identity information based on the ephemeral decryption key and the ephemeral credential at least by the user device, the displayless networking device application server, and a security server.

Cyber security authentication method for displayless networking device

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Semiconductor device and manufacturing method thereof

A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

The fin structure includes a first portion and a second, lower portion separated at a transition. The first portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Fin structure of fin field effect transistor

A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.

Method for monitoring gas in wafer processing system

A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Method for layout generation with constrained hypergraph partitioning

A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.

Efficient analog layout prototyping by layout reuse with routing preservation

An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Method of forming a fin field effect transistor comprising two etching steps to define a fin structure

A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

STI shape near fin bottom of Si fin in bulk FinFET

A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

CMOS device with raised source and drain regions

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Hsinchu, Taiwan

Hung-Ming Chen