Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Lung Lin

Wen-Ju Preet Yang

Li-Sheng Ke

Jia-Rong Hsu

Min-Yuan Tsai

A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

Stretch dummy cell insertion in finFET process

Stretch dummy cell insertion in FinFET process

A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.

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Hsin-Chu, Taiwan

Hung-Lung Lin