Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Hung Lung Lin

Chin-Chang Hsu

Wen-Ju Preet Yang

Chien Lin Ho

Min-Yuan Tsai

Yi-Kan Cheng

Yen-Hung Lin

Cheng-I Huang

Li-Chun Tien

Chung-Hsing Wang

Ken-Hsien Hsieh

Yuan-Te Hou

Huang-Yu Chen

Ting Yu Chen

Tsong-Hua Ou

Hsiao-Shu Chao

Chin-Hsiung Hsu

Ching Fu Chang

Wen-Li Cheng

Yi-Chuin Tsai

Ying-Yu Shen

A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base layout cells, or one of the set of composite layout cells, and constituent layout cells of the one of the set of composite layout cells having been determined as N-colorable. Whether a first candidate cell of the set of candidate cell is N-colorable is determined. An abutment-sensitive conflict graph of the first candidate cell is generated when the first candidate cell is N-colorable and the first candidate cell is not the top layout cell.

Method of determining if layout design is N-colorable

A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

EDA tool and method for conflict detection during multi-patterning lithography

Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Triple-pattern lithography layout decomposition

The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Multi-patterning conflict free integrated circuit design

A method of decomposing a layout for triple pattern lithography generates a first conflict graph from the layout. The method generates a second conflict graph from the first conflict graph, and identifies loops in the second conflict graph as decomposition violations.

Triple-pattern lithography layout decomposition validation

A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

Tool and method for eliminating multi-patterning conflicts

The photo frame contains a frame body, first and second transparent plates, first and second light generating units. The frame body contains a number of side walls and a back cover. The first transparent plate is jointed to the frame body and attached to the back cover with a photo in between. The second transparent plate is arranged to the frame body's front side, parallel to the first transparent plate and forming a gap therebetween. A first light generating unit contains at least a first light generating element configured along a side wall, projecting illuminating light into the gap to create a stereographic impression. The second light generating unit contains at least a second light generating element arranged an edge of the second transparent plate to project blue light into the second transparent plate to manifest fluorescent traces written by a highlighter.

Photo frame with message board function

Disclosed is a mechanically operated razor which does not require any electric power supply while functioning as a power-driven shaver. The razor mainly includes a housing, a driving mechanism, a transmission mechanism, a top cover, a shaving blade, and a mirror. Repeatedly pushing a push button of the driving mechanism toward the housing causes a rack connected the push button to move inward and to mesh with and rotate a gear of the transmission mechanism. The rotating gear in turn brings other gears of the transmission mechanism and a flywheel to rotate, causing the shaving blade to rotate rapidly for a prolonged time. The rotating flywheel may reduce the times the push button is depressed while prolongs the rotating of the shaving blade, so that the razor functions like an electrically driven razor. A cleaning brush is removably attached to the razor for cleaning the razor after shaving. A cotter coupled with a switch button on the push button can be ascended to engage with the top cover when the push button is fully pushed into the housing and the switch button is pushed upward, and thereby retains the entire push button in the housing, allowing the razor to be conveniently stored or carried.

Growing community of inventors

Hsinchu, Taiwan

Hung Lung Lin