Taiwan Semiconductor Manufacturing Comp. Ltd.

Ritdisplay Corporation

Hung-Lin Chen

Shiuan-Jeng Lin

Sheng-Tai Peng

Shih-Chung Chen

Tsung-Lin Lee

Feng-Chi Hung

Hsiu-Mei Yu

Shyh-Wei Cheng

Chin Kun Lan

Kuan-Jung Chen

Cheng-Ping Chen

Man-Kit Leung

Chi-Chih Liao

Ming-Chang Hsieh

Tzu-Chin Tang

Yung-Chih Lee

Kuei-Hui Yang

Yi-Meen Chou

Dong-Lung Lee

Jian-Hsing Lee

Wen-Chih Chiang

Jui-Chun Weng

Shao-Yen Ku

Hua-Shu Ivan Wu

Ren-Dou Lee

Che-Jung Chu

Yu-Jui Wu

Chun-Ming Lin

Tian Sheng Lin

Ya-Jen Sheuh

Tza-Hao Wang

Deng-Shun Chang

Po-Ming Chen

Tzu-Hao Yeh

Yi-Shao Lin

Albion Pan

Bob Sun

Shih-Chin Lee

A polishing pad conditioning apparatus includes a base, a fiber, and a polymer protruding from a surface of the base and encompassing the fiber.

Polishing pad conditioning apparatus

Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Bipolar junction transistor (BJT) and fabricating method thereof

Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

Multi-layered windows for use in chemical-mechanical planarization systems

The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

Alignment mark structure and method for making

A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Fluorine doped non-volatile memory cells and methods for forming the same

A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

Metal-insulator-metal (MIM) capacitor with an electrode scheme for improved manufacturability and reliability

A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.

One-time-programming (OTP) memory cell with floating gate shielding

The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Diffusion region routing for narrow scribe-line devices

A method of manufacturing double diffused drains in a semiconductor device. An embodiment comprises forming a gate dielectric layer on a substrate, and masking and patterning the gate dielectric layer. Once the gate dielectric layer has been patterned, a second dielectric layer, having a different depth than the gate dielectric layer, is deposited into the pattern. Once the dielectric layers have been placed into a step form, DDDs are formed by implanting ions through the two dielectric layers, whose different filtering properties form the DDDS. In another embodiment the implantations through the two dielectric layers are performed using different energies to form the different dose regions. In yet another embodiment the implantations are performed using different species (light and heavy), instead of different energies, to form the different dose regions.

Method of manufacturing double diffused drains in semiconductor devices

An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Electrostatic discharge protection device

A double-diffused-drain metal-oxide-semiconductor device has a gate structure overlying a semiconductor substrate, a pair of insulator spacers on the sidewalls of the gate structure respectively, and a pair of floating non-insulator spacers embedded in the pair of insulator spacers respectively.

Double-diffused-drain MOS device with floating non-insulator spacers

An organic light-emitting diode comprises an anode, an organic electroluminescent layer, a metal doped layer, and a cathode, in sequence, on a substrate; wherein the metal doped layer comprises an organic compound represented by the formula (1) doped with a metal. 

Organic light-emitting diode and material applied thereto

An organic light-emitting diode comprises an anode, an organic electroluminescent layer, a metal doped layer, and a cathode, in sequence, on a substrate; wherein the metal doped layer comprises an organic compound represented by the formula (1) doped with a metal.

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Pingtung, Taiwan

Hung-Lin Chen