Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Li Chiang

Tzu-Chiang Chen

Chao-Ching Cheng

I-Sheng Chen

Yee-Chia Yeo

Chih Chieh Yeh

Cheng-Yi Peng

Szu-Wei Huang

Tsung-Lin Lee

Yu-Lin Yang

Yu-Sheng Chen

Jer-Fu Wang

Jung-Piao Chiu

Chih-Sheng Chang

Lain-Jong Li

Feng Yuan

Huan-Sheng Wei

Yi-Tse Hung

Chun-Chieh Lu

Chih-Liang Chen

Meng-Fan Chang

Chih-Chieh Yeh

Wei-Jen Lai

Tung-Ying Lee

Chung-Cheng Wu

Hung-Ming Chen

Jyh-Cherng Sheu

Shih-Syuan Huang

Chi-Wen Liu

Cheng-Hsien Wu

Yen-Ming Chen

Tsung-Yao Wen

Chi On Chui

Zhiqiang Wu

Sung-Li Wang

Ta-Pen Guo

Ying-Keung Leung

Yi-Ming Sheu

Jin Cai

Chia-Wen Liu

Lei-Chun Chou

Hon-Sum Philip Wong

Ming-Yang Li

Ang-Sheng Chou

Sai-Hooi Yeong

Jhon-Jhy Liaw

Kuo-Hua Pan

Wen-Hsing Hsieh

Xinyu Bao

Ta-Chun Lin

Yu-Chao Lin

Jon-Hsu Ho

Tse-An Chen

Ming-Yuan Song

Kuo-Cheng Chiang

Chung-Te Lin

Carlos H Diaz

Yih Wang

Shy-Jay Lin

Jin-Aun Ng

Kai-Tai Chang

Tzu-Ang Chao

Katherine H Chiang

Shao-Ming Yu

Chia-Cheng Ho

Chi-On Chui

Yu-sheng Chen

A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.

Memory devices

An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Self-aligned contact for embedded memory

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and multiple nanostructures over the substrate. The semiconductor device structure also includes a semiconductor fin between the substrate and the nanostructures. The semiconductor device structure further includes a gate stack wrapped around the nanostructures. The gate stack includes a gate dielectric layer, and the gate dielectric layer continuously extends along a bottommost nanostructure of the nanostructures and an upper portion of the semiconductor fin.

Semiconductor device structure with hybrid fins

A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

Memory devices and methods of forming the same

A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

3T memory with enhanced speed of operation and data retention

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Semiconductor device

Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

Data storage element and manufacturing method thereof

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional '2D' semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Forming semiconductor structures with two-dimensional materials

The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Isolation structures of semiconductor devices

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

Resistive memory devices using a carbon-based conductor line and methods for forming the same

A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.

SRAM memory cell device comprising ferroelectric access and storage transistors

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Semiconductor device and manufacturing method thereof

A memory device is provided. The memory device includes a bottom electrode, a first data storage layer, a second data storage layer, an interfacial conductive layer and a top electrode. The first data storage layer is disposed on the bottom electrode and in contact with the bottom electrode. The second data storage layer is disposed over the first data storage layer. The interfacial conductive layer is disposed between the first data storage layer and the second data storage layer. The top electrode is disposed over the second data storage layer.

Memory device and operating method thereof

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. The dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.

Semiconductor device structure with nanostructure

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Taipei, Taiwan

Hung-Li Chiang