Aspeed Technology Inc.

Silicon Integrated Systems Corporation

Hung-Ju Huang

Hung-Ming Lin

Chung-Yen Lu

Fu-Chou Hsu

Hung-Ta Pai

Jo-Tan Yao

Yung-Ching Chang

Chun-An Tu

Ching-Mei Huang

Shu-An Huang Ho

Jen-Min Yuan

Ya-Cheng Chen

Chung-Heng Chen

Ming-Chi Pai

The disclosure provides an integrated circuit and an operation method and an inspection method thereof. The integrated circuit includes a one-time programmable (OTP) memory, an identifier generation circuit, and a memory controller. The identifier generation circuit generates a random number, and performs an error-detection-code encoding operation on the random number to generate an identifier with an error-detection code. The memory controller writes the identifier generated by the identifier generation circuit into the OTP memory. The identifier generation circuit reads the identifier from the OTP memory through the memory controller, and performs an error-detection-code decoding operation on the identifier provided by the memory controller to determine whether an error of the identifier from the OTP memory is correctable. When it is determined that the error of the identifier from the OTP memory is not correctable, the writing of the identifier is deemed failed.

Integrated circuit and operation method and inspection method thereof

A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first multiplexer and a second multiplexer. The first UART controller and the second UART controller have different baud rates. The UART port has a R&#xd7;D pin coupled to a R&#xd7;D pin of the second UART controller. The debug controller generates a control signal with a first state and checks whether a received data from the UART controller is equal to a keyword after power-up or a hardware reset. When the received data from the second UART controller is equal to the keyword, the debug controller generates the control signal with the second state, and starts parsing and executing at least one debug command from the second UART controller.

System on chip with debug controller and operating method thereof

A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

High speed baseboard management controller and transmission method thereof

An integrated circuit with automatic configuration is disclosed. The integrated circuit comprises a plurality of controllers and a clock detection device. The controllers share a plurality of common pins. The clock detection device coupled to a specified common pin for performing clock detection operations on an external clock signal through the specified common pin according to a plurality of predetermined thresholds and generating a plurality of control signals to the controllers so that only one controller is enabled and performs signal transmission through the common pins.

Integrated circuit with automatic configuration and method thereof

The invention discloses a transmitting apparatus. The transmitting apparatus uses the same transmission medium to transmit two signals that are within different frequency ranges at the same time. The transmitting apparatus increases the transmitting paths of the transmission medium so as to enhance the use of the transmission medium and save the production costs.

Transmitting device

The present invention provides a remote control system for a power supply, comprising: a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply.

Method for remote power control and the circuit thereof

A progressive differential motion JPEG codec is disclosed. The compression encoder of the progressive differential motion JPEG codec comprises a video capture unit, a video capture buffer, a detection unit, a compression unit, and a quality level buffer. The video capture unit is used for receiving an image data and dividing a component of the image data into a plurality of image data blocks. The video capture buffer stores the image data block. The detection unit is electrically coupled to the video capture unit and the video capture buffer for detecting whether a content of the image data block input from the video capture unit is different from a content of the image data block retrieved from the video capture buffer. The compression unit is electrically coupled to the detection unit for compressing the image data block retrieved from the video capture buffer with a predetermined level compression scheme depending on the difference between the content of the image data block input from the video capture unit and the content of the image data block retrieved from the video capture buffer. The quality level buffer assigns and stores an index value indicative of level compression scheme in the quality level buffer when the compression unit compresses the image data block retrieved from the video capture buffer.

Progressive differential motion JPEG codec

A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.

Method and apparatus for improving depth information communication bandwidth in a computer graphics system

An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Apparatus and method for automatic determination of operating frequency with built-in self-test

A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Digital clock throttling means

A method for contrast enhancement of pixel data of a decompressed color image includes the steps of computing I component values in an HSI color space for the pixel data of the color image, computing an image I component value which is an average of the computed I component values, and enhancing each of the pixel data of the color image according to the image I component value. An apparatus for contrast enhancement of pixel data of a decompressed color image is also disclosed.

Method and apparatus for contrast enhancement of color images

A method and system for compressing graphic data by dividing the data into segments is disclosed. The size of the divided segment is programmable. A frame buffer partitioned into a compressed frame buffer and an uncompressed frame buffer stores graphic data. Each segment of the graphic data is compressed by three different algorithms that encode the graphic data as a plurality of code-words. Each code-word for the segment is taken from the algorithm that can compress the largest number of pixels in the code-word. A header is used to indicate the number of code-words and the compression method used in each code-word. The total number of bytes obtained from the compression of a segment is compared to a pre-defined limit to determine if the compression of the segment is successful. The successfully compressed data of a segment are written to the compressed frame buffer. A compression status flag buffer is used to identify if a segment is compressed or not. A decompressor decompresses or passes the graphic data to a pixel stream for display according to the compress status flag.

Method and system for segment encoded graphic data compression

A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.

Growing community of inventors

Hsinchu, Taiwan

Hung-Ju Huang