Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Ju Chien

Ying-Lang Wang

Wen-Kung Cheng

Chun-Ching Tsan

Hsi-Kuei Cheng

Jowei Dun

Hsien-Ping Feng

Shih-Tzung Chang

Chin-Hao Su

Chu-Chang Chen

Yin-Lang Wang

Hsun-Chang Chan

Chen-Hua Douglas Yu

Chung-Shi Liu

Shau-Lin Shue

Yuan-Hung Chiu

Chun-Chang Chen

Ying-Hsiang Chen

Been-Hon Lin

Jin-Chang Chen

Chin-Chung Lee

Chia-Cheng Wang

An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

Semiconductor devices having post passivation interconnections and a buffer layer

A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Method for reducing defects in post passivation interconnect process

An improved and new process for separating a substrate from a wetted polishing pad in a CMP apparatus has been developed. Following CMP the polishing pad is wetted with a low surface tension liquid and the substrate is moved across the surface of the polishing pad to cause the interface between the substrate and the polishing pad to be wetted with the low surface tension liquid. The force required to cause separation of the substrate from the polishing pad wetted with said low surface tension liquid is reduced by a factor of about 10 to 30% and the breakage of fragile semiconductor wafer substrates during the unloading operation is markedly reduced. Suitable low surface tension liquids are water at a temperature between about 50&deg; C. and 80&deg; C., or solutions of water with long chain surfactants, such as poly-acrylate, poly-vinyl alcohol, butanol, pantanol or isopropol alcohol.

Method of unloading substrates in chemical-mechanical polishing apparatus

A template for measuring the edge width on a disk that is not covered by a coating layer on a top surface of the disk and a method for using such template are disclosed. The template is made of a substantially transparent sheet that has a contour substantially the same as the contour of the disk to be measured. A series of marks are provided on a top surface of the sheet along a peripheral edge of the sheet at numerous predetermined distances from the peripheral edge. The marks may be provided in scribed thin lines, or the marks may be provided in scribed thin lines that are color coded for easier identification purpose. The present invention novel template can be most suitably used on a silicon wafer of any size. However, it can also be used on a disk of any shape or contour to produce the same desirable result.

Template for measuring edge width and method of using

A semiconductor wafer having a double inter-metal dielectric layer formed in the gaps of and on closely. spaced metal interconnection circuitry. The double dielectric layer is formed by an in situ low temperature two step deposition HDP-CVD process separated by a cool-down period. The low temperature process mitigates metal line defects such as distortion or warping caused by heat generated during the process of filling gaps having aspect ratios greater than 2. The double dielectric layer is composed of Group IV materials, silicon being the preferred material. These double layers may be individually doped. Titanium nitride layers, present as by-products of seeding and anti-reflective coatings serve to reduce electro-migration of the metal circuitry.

Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry

A method for detecting leakage in a bellow-type flow control valve and an apparatus for use in such detection are described. In the method, a leakage detection device can be connected in line and in fluid communication between a shut-off valve and a bellow-type flow control valve. The leakage detection device includes a mass flow controller and a recording means for detecting any possible leakage of a facility gas that is used to open or close the bellow-type flow control valve into a process gas conduit through a defective bellow. The apparatus may be advantageously equipped with quick disconnect fittings such that it can be used for checking a large number of bellow-type flow control valves that are normally used on a semiconductor fabrication apparatus.

Method and apparatus for detecting leakage in a flow control valve

A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.

PE-silane oxide particle performance improvement

This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.

Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry

A new method of forming a plasma-enhanced silicon-rich oxynitride layer having improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity by using argon as the inert carrier gas is described. A semiconductor substrate is provided which may include semiconductor device structures. An Argon-based silicon-rich oxynitride etch stop layer is deposited overlying the semiconductor substrate. An oxide layer is deposited overlying the Argon-based silicon-rich oxynitride etch stop layer. An opening is etched through the oxide layer stopping at the Argon-based silicon-rich oxynitride etch stop layer. Thereafter, the Argon-based silicon-rich oxynitride etch stop layer within the opening is removed. The opening is filled with a conducting layer. This Argon-based silicon-rich oxynitride layer has improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity as compared with a helium-based silicon-rich oxynitride layer.

Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer

A method for increasing electromigration resistance within the metal stack layer of Wolfram plugs by applying air exposure or plasma treatment to the top surface of the first layer of metal within the metal stack layer that is formed on top of metal plugs. The remainder of the process of the formation of the metal stack layer is not affected by the present invention.

Method of improving metal stack reliability

A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.

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Hsin-Chu, Taiwan

Hung-Ju Chien