Winbond Electronics Corporation

Hung-Hsueh Lin

Hsin-Chang Lin

Kow-Liang Wen

A current sensing circuit including a differential sensing amplifier and a pre-charging circuit is provided. The differential sensing amplifier includes a first input end, a second input end and a output end. The first input end is coupled to a selected cell via a first data line. The second input end is coupled to a reference cell via a second data line. The output end outputs a sensing data of the selected cell. The pre-charging circuit is coupled to the differential sensing amplifier. The pre-charging circuit is configured to provide a pre-charging circuit and perform a pre-charging operation on the first data line. The first data line has a cell current and the pre-charging circuit. The second data line has a reference current. The pre-charging circuit is determined according to the reference current.

Current sensing circuit using proportional current mirrors

A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of well regions. Each of the well regions includes a plurality of memory blocks and a record block. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation on the memory blocks of each of the well regions and record erase times of each of the well regions into the respective record block. In addition, a method for operating a flash memory storage device is also provided.

Flash memory storage device and method thereof

A byte-programming method for programming data from a page register to a non-volatile memory array includes reading data of a selected byte in the page register and programming the data to the memory cells of the non-volatile memory corresponding to a selected column address; determining whether to update an array column address according to the selected column address, which includes: determining whether the data of the selected byte matches specified content; when the data of the selected byte matches the specified content, not updating the array column address; and when the data of the selected byte does not match the specified content, updating the array column address according to the selected column address; and determining whether the selected column address is the last column address.

Fast programming methods for flash memory devices

A current-sensing circuit for a memory and a sensing method thereof are provided. The current-sensing circuit includes a pre-charge circuit, a sensing current-to-voltage generator, an auxiliary current-to-voltage generator, a reference current-to-voltage generator, and a detection circuit. The pre-charge circuit provides a pre-charge signal to a selected bit line during a pre-charge time period. The sensing current-to-voltage generator generates a sensing voltage to a memory cell current of the selected bit line via a first load. The auxiliary current-to-voltage generator provides a detection voltage to a portion of the memory cell current of the selected bit line via a second load. The reference current-to-voltage generator provides a reference voltage during a data-sensing time period. The detection circuit determines an end time point of the pre-charge time period by comparing a detected voltage generated by the second load with a reference voltage.

Current-sensing circuit for memory and sensing method thereof

An erase method for a flash memory is provided. First memory cells of the flash memory are pre-programmed. The first memory cells are disposed in a memory array formed by a plurality of row and column lines. The programmed first memory cells are erased. The erased first memory cells are post-programmed, to repair the over-erased first memory cells. Second memory cells are programmed after the erased first memory cells are post-programmed. The second memory cells are disposed in a first specific column line of the memory array. The first specific column line is arranged after a last column line corresponding to a last valid column address. Third memory cells disposed in a second specific column line of the memory array. The second specific column line is arranged after the last column line and is adjacent to the first specific column line.

Erase method for flash

A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal.

IAS voltage generator for reference cell and bias voltage providing method therefor

A reading device for a memory array is provided. The memory array comprises memory cell columns. The reading device comprises first sensing amplifier groups, a second sensing amplifier group, and an output unit. Each first sensing amplifier groups selectively generates a first sensing output signal. The second sensing amplifier group generates a second sensing output signal. The output unit selectively outputs one of the second sensing output signal and the first sensing output signals according to a page address signal. In a reading operation period, the reading device reads data from a column group to the first sensing amplifier groups. In the reading operation period, when the page address signal indicates an initial input address, initial address data read from the specific column set corresponding to the initial input address among the column group is transmitted to the second sensing amplifier group to generate the second sensing output signal.

Reading devices for memory arrays

A high storage capacity, wide data channel SRAM having a 64-bit wide data input/output channel, 4 Mbyte or 2 Mbyte of memory, and packaged as a 100-pin QFP or TQFP. The SRAM can be a substitute for a conventional 128 pin QFP or TQFP SRAM because all the functions including pipeline burst transmission are present. Moreover, the SRAM has a comparatively lower package testing and production cost.

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Taichung, Taiwan

Hung-Hsueh Lin