Advanced Semiconductor Engineering, Inc.

Hung-Hsiang Cheng

Chih-Yi Huang

Guo-Cheng Liao

Chih-Wei Wu

Yun-Hsiang Tien

Tzu-Chih Lin

Ting Ruei Chen

Chang-Ying Hung

A semiconductor device package includes a substrate, an air cavity, a radiator, and a director. The substrate has a top surface. The air cavity is disposed within the substrate. The air cavity has a first sidewall and a second sidewall opposite to the first sidewall. The radiator is disposed adjacent to the first sidewall of the air cavity. The director is disposed adjacent to the second sidewall of the air cavity.

Semiconductor device package

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate having a first surface and a second surface opposite to the first surface, an antenna module disposed on the first surface of the first substrate, an electronic component module disposed on the first surface of the first substrate, and a first package body encapsulating the antenna module and the electronic component module. The antenna module has a first surface facing the first surface of the first substrate, a second surface opposite to the first surface of the antenna module, and a lateral surface extending between the first surface of the antenna module and the second surface of the antenna module. The lateral surface of the antenna module faces the electronic component module. A method of manufacturing a semiconductor device package is also provided.

The present disclosure relates to a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.

The present invention relates to a semiconductor device having a shielding layer. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.

Semiconductor device having shielded conductive vias

The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Method of making semiconductor package having redistribution layer

The present invention relates to a circuit substrate having a first conductive layer. The first conductive layer includes at least one power/ground plane. The power/ground plane includes at least one plane edge and plurality of grid lines. Each grid line has a width. The grid lines intersect each other to define a plurality of first grid holes, wherein the distance between the first grid hole that is closest to the plane edge and the plane edge is 1.5 times the width. Thus, the influence on the resistance of power signal and ground signal caused by the first grid holes is reduced, power integrity is improved, and heat generation is reduced.

Circuit substrate having power/ground plane with grid holes

A semiconductor package and a method for making the same, whereby the semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, and second and third metal layers. The substrate has a surface having at least first and second pads. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Semiconductor package having redistribution layer

A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.

Multi-layer circuit board having ground shielding walls

Carrier with solid antenna structure comprises a substrate and at least one solid antenna structure. The substrate has an upper surface, a lower surface, at least one first slot communicating with the upper surface and the lower surface and at least one second slot communicating with the upper surface and the lower surface. The solid antenna structure has a dielectric block formed between the first slot and the second slot and a radiation conductor, in which the dielectric block encloses the radiation conductor. In this invention, the solid antenna structure is used to enable the carrier to be applied to higher power transmission. Additionally, by setting the material of the dielectric block and optimizing the size of the radiation conductor, the carrier can be applied to multi-band.

Growing community of inventors

Kaohsiung, Taiwan

Hung-Hsiang Cheng