Texas Instruments Corporation

Hung-Dah Shih

Donald L Plumton

Han-Tzong Yuan

Hisashi Shichijo

Bumman Kim

Liem T Tran

Tommy J Bennett

Paul Saunier

A method and apparatus (10) for forming a p-doped layer (68, 80, 92) of Group II and Group VI elements by molecular beam epitaxial process in which a nitrogen dopant is introduced as the layer (68, 80, 92) is being grown. In one embodiment, molecular nitrogen is passed through a plasma generator (46) for convening it to activated nitrogen, and the activated nitrogen is conducted through an elongated guide tube (50) toward the substrate (66) upon which a Group II-Group VI layer (68, 80, 92) is being grown. In one embodiment, an n-type dopant source (72) is also provided, the apparatus (10) being operable for forming electrical devices (86, 88) having successive layers (78, 80, 90, 92, 94) of differing electrical characteristics.

Apparatus for p-type doping of semiconductor structures formed of group

A method and apparatus (10) for forming a p-doped layer (68, 80, 92) of Group II and Group VI elements by molecular beam epitaxial process in which a nitrogen dopant is introduced as the layer (68, 80, 92) is being grown. In one embodiment, molecular nitrogen is passed through a plasma generator (46) for converting it to activated nitrogen, and the activated nitrogen is conducted through an elongated guide tube (50) toward the substrate (66) upon which a Group II-Group VI layer (68, 80, 92) is being grown. In one embodiment, an n-type dopant source (72) is also provided, the apparatus (10) being operable for forming electrical devices (86, 88) having successive layers (78, 80, 90, 92, 94) of differing electrical characteristics.

Method for p-type doping of semiconductor structures formed of group II

Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Method of making complementary heterostructure field effect transistors

Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

Complementary heterostructure field effect transistors

A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudomorphic material. There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.

Method of forming heterostructure field effect transistor

A heterostructure field effect transistor having a buffer layer comprising a first compound semiconductor material. A layer of second semiconductor material different from the first material is formed over the buffer layer. The second layer has a total thickness less than 250 .ANG.. A doped third semiconductor layer formed over the second layer. The net has a dopant concentration in the second layer is greater than the net dopant concentration in the third layer. A gate layer is positioned over the third layer. In a preferred embodiment the second layer is a pulse-doped pseudeomorphic material. There is also provided a method for making the heterostructure field effect transistor. A doped pseudomorphic semiconductor layer of a first conductivity type is formed between first and second other semiconductor layers, the second layer including a net dopant concentration of the first conductivity type. A Schottky gate electrode is formed in contact with the second layer.

Heterostructure field effect transistor

Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.

Method for selective epitaxy using a WS.sub.I mask

Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small, isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectively grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirrors being the sidewalls of the vertical structures.

Selective epitaxy devices and method

A molecular beam epitaxial growth process, for growth of III-V compounds, wherein a substrate is heated approximately to growth temperature before the group III cell is fully heated. That is, for example, to grow gallium arsenide, the arsenic cell would be heated, the arsenic cell's shutter opened, and the substrate heated up to growth temperature (e.g. 600 C), before the gallium cell is heated up. After the gallium cell is heated up, its shutter is opened, and epitaxial growth proceeds.

Molecular beam epitaxial process

A molecular beam epitaxy system wherein the molybdenum substrate holder and the molybdenum ring which assembles to the substrate holder to hold the wafer are kept in vacuum essentially all the time. Wafers are not pre-mounted to substrate holders, but the wafer mounting step is performed in ultrahigh vacuum after a cassette of wafers has already been loaded and outgassed, under ultrahigh vacuum. Thus, the substrate holder can be outgassed separately at high temperatures, and can remain under high vacuum.

MBE system with in-situ mounting

A molecular beam epitaxy system wherein the wafer on which epitaxial deposition is to occur is not soldered to a substrate holder. Instead, a substrate holder with a lip approximately as high as the thickness of the wafer is used, and a retaining ring attaches to the substrate holder to hold the wafer in place during the growth cycle. The retaining ring, like the substrate holder, is made of high-purity refractory material, such as arccast molybdenum. The substrate holder and retaining ring are dimensioned to hold the wafer somewhat loosely, to allow for thermal expansion during the cycling up to growth temperature, which is typically about 600.degree. C.

Solderless MBE system

A molecular beam epitaxy system including a growth chamber and an analysis chamber, both connected to ultrahigh vacuum pump systems. The analysis chamber includes a source outgassing mount, so that, while growth is proceeding in the growth chamber, a newly received source can be outgassed in the special mount connected to the analysis chamber. Preferably the exhausted cryogenic gases from the cryo shield in the growth chamber are used to cool the source outgassing mount on the analysis chamber, to minimize the contamination of the analysis chamber by contaminants outgassed.

MBE Source bakeout system

A multiple high electron mobility transistor structure without inverted heterojunctions is disclosed. Multiple normal heterojunctions of doped aluminum gallium arsenide grown on gallium arsenide without alternating inverted heterojunctions of gallium arsenide grown on doped aluminum gallium arsenide is achieved by grading undoped aluminum gallium arsenide from the doped aluminum gallium arsenide to the gallium arsenide to avoid an inverted heterojunction.

Growing community of inventors

Plano, TX, United States of America

Hung-Dah Shih