Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Hung-Chung Chien

Li-Duan Tsai

Ming-Feng Shieh

Yi-Chang Du

Hung-Chang Hsieh

Chih-Chieh Yang

Shu-Fang Chen

Hao-Ken Hung

Jhun Hua Chen

Chun-Ming Hu

Lin-Hung Shiu

Yong-Hong Liao

Chao-Hong Chen

A device includes a diffraction-based overlay (DBO) mark having an upper-layer pattern disposed over a lower-layer pattern, and having smallest dimension greater than about 5 micrometers. The device further includes a calibration mark having an upper-layer pattern disposed over a lower-layer pattern, positioned substantially at a center of the DBO mark, and having smallest dimension less than about ⅕ the size of the smallest dimension of the DBO mark.

Alignment mark and method

A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Semiconductor device with backside power rail and method for forming the same

Semiconductor processing apparatuses and methods are provided in which a semiconductor wafer is flipped and then rotated between patterning of front and back sides of the semiconductor wafer by first and second reticles, respectively. In some embodiments, a method includes patterning, by a first reticle, a first layer on a first side of a semiconductor wafer while the first side of the semiconductor wafer is facing a first direction. The semiconductor wafer is then flipped. A second side of the semiconductor wafer that is opposite the first side faces the first direction after the flipping the semiconductor wafer. The semiconductor wafer is then rotated about a rotational axis extending along the first direction, and a second layer on the second side of the semiconductor wafer is patterned by a second reticle.

System and method for overlay error reduction

A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.

Lithography method with surface modification layer

The present disclosure provides a semiconductor fabrication method. The method includes modifying an edge portion of a wafer such that the edge portion are prevented from resist coating; coating a resist layer on the front surface of the wafer, wherein the resist layer is free from the edge portion of the wafer; and performing an exposing process to the resist layer.

Semiconductor method with wafer edge modification

Provided is a composite electrode including a metal layer and a composite dielectric layer. The composite dielectric layer includes a metal oxide dielectric layer and a polymer dielectric layer. The composite dielectric layer overlays the metal layer. The polymer dielectric layer includes a nitrogen-containing polymer and overlays the metal oxide dielectric layer. An electrolytic capacitor is also provided. The electrolytic capacitor has a polymer dielectric layer made of a nitrogen-containing polymer, and such polymer dielectric layer is beneficial to increase the insulating property of the metal oxide dielectric layer and the coverage property of the conductive polymer. Thereby, the conventional leakage current can be significantly reduced and the yield can be improved.

Composite electrode and electrolytic capacitor

An electrolyte mixture for electrolytic capacitor is disclosed. The electrolyte mixture includes a conductive polymer and a nitrogen-containing polymer. The nitrogen-containing polymer includes a cyclic nitrogen-containing polymer, a polymer with primary amine group, a polymer with secondary amine group, a polymer with tertiary amine group, a polymer with quaternary ammonium group, or a combination thereof.

Electrolyte mixture for electrolytic capacitor, composition for conductive polymer synthesis and conductive polymer solid electrolytic capacitor formed by using the same

An electrolyte mixture for an electrolytic capacitor is provided. The electrolyte mixture includes a conjugated polymer, a polyether and a nitrogen-containing compound, or includes the conjugated polymer, the polyether and a nitrogen-containing polymer, or includes the conjugated polymer and a polyether with nitrogen-containing functional groups. The electrolyte mixture provides a very high static capacitance for an electrolytic capacitor having the same.

Electrolyte mixture, electrolytic capacitor having the same and oxidant mixture for conjugated polymer synthesis

A composite proton exchange membrane is made up of dispersed organized graphene in ion conducting polymer as a fuel barrier material. The composite proton exchange membrane includes an inorganic material of 0.001-10 wt % and an organic material of 99.999-90 wt %. The inorganic material is a graphene derivative with two-dimensional structure. The organic material includes a polymer material with sulfonic acid group.

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Chiayi County, Taiwan

Hung-Chung Chien