Silicon Integrated Systems Corporation

Hung-Chih Liu

Wei-Chen Shen

Stanley Liao

Sheng-Yeh Lai

Zwei-Mei Lee

Hsian-Feng Liu

Chi-Tai Yao

Hsien-Feng Liu

Ching-Lin Wu

Jieh-Tsomg Wu

A squelch circuit for operating at high speed and at high frequencies includes a squelch input unit, a low swing pre-amplifier and a sampling and decision circuit. The squelch input unit pre-processes the positive and negative signals of an input signal to generate four pre-processed signals that are paired and sent to the low swing pre-amplifier. The outputs of the low-swing pre-amplifier are then over-sampled by the sampling and decision circuit. Multi-phase clocks are used to control the over-sampling in the sampling and decision circuit. A logic circuit then determines if the state of the input signal based on multiple samples.

Squelch circuitry for high speed high frequency operation

A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Background-calibrating pipelined analog-to-digital converter

A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

Current output circuit for use in digital-to-analog converter

The present invention discloses a current feedback operational amplifier, whose input ends are connected to a first amplifier which transmits an output to the gate terminals of at least one input pair of current switches, and the source terminal of one transistor of the input pair of current switches is connected to one of the input ends. Therefore, a negative feedback loop will be established by the first amplifier and the input pair of current switches. By means of the negative feedback loop, the input impedance, offset voltage and gain error are all reduced. The input impedance of the present invention is reduced as 1/1&plus;A times as the original one. Therefore, the aspect ratio of the transistors of the input pair of current switches is reduced.

Current feedback operational amplifier

The present invention discloses a DC offset canceling circuit applied in a variable gain amplifier. The DC offset canceling circuit comprises a transconductance amplifier and at least one internal capacitor to function as a filter. The input of the transconductance amplifier is electrically connected to the output of the variable gain amplifier, and the output of the transconductance amplifier and the at least one internal capacitor are electrically connected to the input of the variable gain amplifier to form a feedback loop. To cooperate with the function of the DC offset cancelation, the input stage of the variable gain amplifier comprises an auxiliary differential pair.

DC offset cancelling circuit applied in a variable gain amplifier

A fully differential double edge triggered flip-flop stores and outputs first and second fully differential input values on leading and trailing edges of a clock. The flip-flop includes a first fully differential master circuit, a second fully differential master circuit and a fully differential slave circuit. The first master circuit stores the first input value during the period from the leading edge to trailing edge of the clock. The second master circuit stores the second input value during the period from the trailing edge to leading edge of the clock. The slave circuit is electrically connected to outputs of the first and second master circuits. The slave circuit includes a second repeater as an output end of the flip-flop, outputs the first input value on the trailing edge of the clock, and outputs the second input value on the leading edge of the clock.

Growing community of inventors

Hsinchu, Taiwan

Hung-Chih Liu