Xilinx, Inc.

Other

Hung-Cheng Hsieh

William S Carter

Ross H Freeman

Edmond Y Cheung

Charles S Erickson

Charles R Erickson

Khue Duong

Ross H Freeman, Deceased

This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Circuit for selecting a bit in a look-up table

Distributed memory architecture for a configurable logic array and

Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

Logic structure and circuit for fast carry

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

Memory cell with known state on power up

A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.

Programmable connector for programmable logic device

A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage level returns to above the predetermined voltage. The voltage level sensing circuit is comprised of two inverters and a filter circuit. The inverters start to conduct at different power supply voltage levels and have different trigger point characteristics. The power supply voltage level sensing circuit may be coupled with a power-on reset circuit to create a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first supplied to the circuit, but also when the power supply voltage level temporarily falls below a selected value.

Power supply voltage level sensing circuit

A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

Buffered routing element for a user programmable logic device

A bidirectional buffer having a high impedance state is provided. This buffer is used for amplifying a signal as it is passed from one transmission line to another when it is desirable to select which direction the signal will flow. A switching circuit controls which transmission line is connected to the input terminal of the buffer and which is connected to the output terminal. A high impedance state is also provided for disconnecting the two transmission lines. Two memory cells control the direction of signal flow and the high impedance state.

Three-state bidirectional buffer

5-transistor memory cell with known state on power-up

A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysteresis to improve the noise immunity of the system. The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As a result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.

TTL/CMOS compatible input buffer

A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

TTL/CMOS compatible input buffer with Schmitt trigger

A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to read. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.

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Sunnyvale, CA, United States of America

Hung-Cheng Hsieh