Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

TSMC Solid State Lighting Ltd.

Hung-Chao Kao

Dian-Hau Chen

Hsiang-Ku Shen

Yen-Ming Chen

Hui-Chi Chen

Chih-Fan Huang

Tsung-Chieh Hsiao

Yuan-Yang Hsiao

Ming-I Wang

Yu-Tsung Lin

Hung-Yi Kuo

Fu-Chih Yang

Chih-Kuang Yu

Hsin-Ping Wu

Jin-Mu Yin

Ken Wen-Chien Fu

Ming-Feng Wu

Shouli Steve Hsia

Kuo-Yuh Yang

Chen-Chiu Huang

Liang-Wei Wang

Yu-Jen Wang

Chih-Pin Chiu

Chih-Chuan Su

Tzu-Ting Liu

The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.

Metal-insulator-metal structure and methods of fabrication thereof

A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.

Method of forming a stress reduction structure for metal-insulator-metal capacitors

A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.

Semiconductor memory structure and method for forming the semiconductor memory structure

The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Stress reduction structure for metal-insulator-metal capacitors

The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.

Methods of forming a 3-dimensional metal-insulator-metal super high density (3D-MIM-SHD) capacitor and semiconductor device are disclosed herein. A method includes depositing a base layer of a first dielectric material over a semiconductor substrate and etching a series of recesses in the base layer. Once the series of recesses have been etched into the base layer, a series of conductive layers and dielectric layers may be deposited within the series of recesses to form a three dimensional corrugated stack of conductive layers separated by the dielectric layers. A first contact plug may be formed through a middle conductive layer of the corrugated stack and a second contact plug may be formed through a top conductive layer and a bottom conductive layer of the corrugated stack. The contact plugs electrically couple the conductive layers to one or more active devices of the semiconductor substrate.

Semiconductor device including a high density MIM capacitor and method

A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.

A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer.

LED structure

LED structure having embedded zener diode

An image sensor with at least one correcting lens and a method for fabricating the same are described. The image sensor includes a substrate with an array of microlenses thereon and at least one correcting lens disposed over the substrate covering the microlens array. In the fabricating method, a substrate having formed with a microlens array thereon is provided, and then at least one correcting lens is disposed over the substrate covering the microlens array. The at least one correcting lens can, in use of the image sensor, shift the incident direction of light to a microlens in edge parts of the array of microlenses toward the normal line direction of the image sensor.

Image sensor with correcting lens and fabrication thereof

The present disclosure provides a contiguous microlens array, which consists of a plurality of touching microlenses, wherein the adjacent microlenses are connected to each other to form a contiguous microlens array and curvatures of every angle cross section of each microlens are the same. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto.

Contiguous microlens array

A method of fabricating a contiguous microlens array is disclosed. First, an array of photoresist patterns is formed, wherein each photoresist pattern has a substantially circular or polygonal shape in a top view and neighboring photoresist patterns are connected with each other or close to each other. Then a reflow step is performed to heat the photoresist patterns thereby rounding a surface of each photoresist pattern and connecting the neighboring photoresist patterns that are close to each other. Finally, a fixing step is performed to fix a shape of each photoresist pattern. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto.

Method of fabricating contiguous microlens array

A contiguous microlens array including a plurality of contiguous microlenses is described. Each microlens has substantially circular contours at the heights higher than the connection sections of the microlens with neighboring microlenses, and has substantially partially circular contours at the heights on the connection sections adjacent to the neighboring microlenses. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto.

Growing community of inventors

Taipei, Taiwan

Hung-Chao Kao