Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Chang Yu

Kai-Chun Lin

Yue-Der Chih

Ku-Feng Lin

Yu-Der Chih

Ta-Ching Yeh

Chun-Jung Lin

Chin-Yi Huang

Ying-Hao Kuo

Chia-Fu Lee

Wen-Chin Lin

Yuan-Long Siao

Laun C Tran

Kwan-Jen Chu

Tien-Wei Chiang

Ya-Chen Kao

Chien-Fan Wang

Fei-Wen Cheng

A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.

Method and memory device with increased read and write margin

A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.

Circuit and method to enhance efficiency of memory

A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the amplifier; an array of bit lines connected to corresponding memory cells; and an intra-sense-amplifier recycling arrangement configured to do as follows including: recovering a first charge from a first bit line associated with a first one of the memory cells, the first charge being associated with a preceding first evaluation performed by the sense amplifier; and boosting the branched line to a reference voltage including reusing the first charge to at least partially charge the branched line; and wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference voltage.

Memory device with charge-recycling arrangement

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Method for enhancing tunnel magnetoresistance in memory device

A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell for a memory operation. The reference voltage generator is configured to generate a reference voltage based on at least one of a temperature of the memory array or a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage.

A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of memory cells; an array of bit lines connected to corresponding memory cells in the array of memory cells; a multiplexer configured to selectively connect the branched line to a selected one in the array of memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.

Memory device with recycling arrangement for gleaned charge

The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

Adjustment circuit for partitioned memory block

A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

A circuit includes: a first node to receive a first current; a first resistive element receiving a first branch current of the first current; first transistors each including a first terminal connected to the second end of the first resistive element; a second resistive element connected to the first node and receiving a second branch current of the first current; a second node to receive a second current; a second transistor including a first terminal, the first terminal of the second transistor connected to the second node and receiving a first branch current of the second current; a third resistive element connected to the second node and receiving a second branch current of the second current; wherein a temperature coefficient is adjusted by a resistance of the second resistive element and a resistance of the third resistive element and corresponding to the first current.

A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.

Resistive memory array and fabricating method thereof

A sense amplifier includes a first sample and hold circuit, a second sample and hold circuit, a latch-type amplifier. The first sample and hold circuit is coupled to a bit line and configured to sample and hold memory cell data during a pre-charge phase of a sensing operation. The second sample and hold circuit is coupled to a reference bit line and configured to sample and hold data of a reference memory cell data during the pre-charge phase of the sensing operation. The latch-type amplifier, coupled to the first sample and hold circuit and the second sample and hold circuit, and configured to compare the memory cell data and the reference cell data during an evaluation phase of the sensing operation to output a sensing signal. The sense amplifier is isolated from the bit line and the reference bit line during the evaluation phase of the sensing operation. A sensing method adapted to a sense amplifier and a non-volatile memory include a sense amplifier are also introduced.

Sense amplifier, sensing method and non-volatile memory using the same

A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.

Memory device and method of operating same

A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.

Growing community of inventors

Hsin-Chu, Taiwan

Hung-Chang Yu