Quantum Corporation

Sigma Designs, Inc.

Lsi Logic Corporation

Neomagic Corporation

Greenvity Communications, Inc.

Hung C Nguyen

William Louis Abbott

Son Hong Ho

Catherine A French

Kenneth E Johnson

Ruoyang Lu

Jayesh Desai

John P Tero

Bruce R Peterson

Ali Dolatshahi Pirooz

Phuc Thanh Tran

Ara Patapoutian

Jifeng Geng

Andrew D Hospodor

John Welsford Brooks

Rui Zhang

Michael G Machado

Thomas D Howell

Brian N Kuo

James P McGrath

Can Tri Nguyen

Matthew P Vea

Jeffrey Herbert Appelbaum

A SCO estimator comprises the following units. A module obtains a first data output by a first unit and copies the first data to obtain copied data. A QAM unit quadrature modulates the copied data into each sub-carrier of each OFDM symbol to regenerate transmitted modulated data. A first phase unit obtains a first phase of each sub-carrier of each OFDM symbol of the modulated data. A second phase unit obtains a second data from a second unit, and obtains a second phase of each sub-carrier of each OFDM symbol of the second data. A comparator generates a comparing result according to the first phase and the second phase of each sub-carrier of each OFDM symbol. A divider divides the comparing result of each sub-carrier by the subcarrier index within each OFDM symbol and the OFDM symbol index of each OFDM symbol. An averaging unit averages the divided comparing result over number of sub-carriers and number of OFDM symbols.

Method of estimating sampling clock offset, a sampling clock offset estimator and a receiver comprising the same

A system connected to power lines in a network includes a wireless component; a wired component interfaced with the power lines; a conversion component coupled to the wireless component and the wired component and performs at least unidirectional conversion of a transmission unit between wireless and wired, the conversion employs only MAC addresses for addressing.

System and method for communications in a network

An ultra wideband receiver, based on multiband orthogonal frequency division multiplexing (MB-OFDM), combines digital data from multiple channels after signal processing and before decoding. The receiver provides a master controller that synthesizes packet synchronization, frame synchronization, and sampling frequency offset information from multiple channels into signals that simultaneously control all channels of the receiver.

Ultra wideband baseband chip with intelligent array radio and method of use thereof

An ultra-wideband clear channel assessment system uses a double-window energy technique for energy detection, which indicates a clear or busy channel.

Clear channel assessment method and system for ultra wideband OFDM

The invention enables automatic gain control in ultra wideband applications over multiple channels and frequency bands.

Digital automatic gain control with parallel/serial interface for multiple antenna ultra wideband OFDM system

A method is presented for packet detection and symbol boundary location using a two-step sign correlation procedure. When the correlation crosses a threshold, a packet detection signal is generated to initiate processing of downstream blocks, and a symbol boundary location signal is generated for use in aligning data during processing.

Synchronization method for symbol boundary detection in UWB-OFDM

A receiver sets weights for an antenna array according to a series of algorithms including an energy algorithm, a least squares algorithm and a least mean square algorithm.

Intelligent array radio architecture

A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded memory buffer while row syndromes are being generated in parallel. The block has rows and columns. Row syndromes are generated on-the-fly as the data is written from the DVD disk to the memory buffer. Row syndrome generation thus requires no memory access cycles. Column syndrome generation is delayed until row correction is completed. Once errors in the rows identified by the row syndromes are corrected, column syndromes are generated. The bytes received from the DVD disk for the current row are accumulated into intermediate row syndromes. Received bytes are accumulated for the row until all of the row's bytes have been received and accumulated. The final accumulated row syndromes are written to the embedded memory buffer for later row error-correction. The row syndromes are later sent from the embedded memory buffer to an error corrector that detects, locates, and corrects any errors in the rows. A separate SRAM buffer for error correction is eliminated even though on-the-fly performance is achieved.

On-the-fly row-syndrome generation for DVD controller ECC

Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched. Once initial sync is made, the bit timing is adjusted when too many pseudo-sync clocks are inserted for sync marks missed due to jitter. An early and a late window around the expected sync point are used to enable re-sync to a detected fixed sync pattern.

Error-tolerant sync detection for DVD optical disks using programmable sequence of sync marks

An optical disk controller reads CD-ROM disks at high speeds that commonly produce errors. Errors in the headers that identify sectors are tolerated by the sector-search hardware. The disk-controller firmware writes a virtual target register the previous sector's header's minutes, seconds, frame (MSF), which is one less that the desired sector's MSF, or MSF-1. A physical target that precedes the virtual target is searched for. The physical target precedes the desired sector by N sectors, so that the physical target is MSF-N. When the physical target matches a header read from the disk, a good sector found flag is set. The physical target is then incremented for each new sector and compared to the virtual target. Once the physical target matches the virtual target, the following sector is buffered to the host. The raw header from the disk is stored and error corrections are made using the error correction byte following the sector's data. The corrected raw header is compared to the virtual target to determine if the correct sector was captured. The virtual target is also incremented so that all following sectors that are transferred to the host can also have their headers checked.

Error-tolerant target-sector search using previous N sector ID for high-speed CD

An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes. The full width is used for writing data from the optical disk to the ECC data block buffer, and for reading data from the host-buffer area to the host. Narrower access widths are used by the error correction and de-scrambler blocks.

DVD controller with embedded DRAM for ECC-block buffering

A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded memory buffer. The block has rows and columns. Row syndromes are generated on-the-fly as the data is written from the DVD disk to the memory buffer. Row syndrome generation thus requires no memory access cycles. Once errors in the rows identified by the row syndromes are corrected, column syndromes are generated. A multi-byte fetch supplies a multi-column syndrome generator with bytes in the row for two or more columns. The fetched bytes for the two or more columns are accumulated into intermediate syndromes. Fetched bytes are accumulated for other rows until all of the column's bytes in all rows have been fetched and accumulated. The final accumulated syndromes are output to an error corrector that detects, locates, and corrects any errors in the columns. The same error corrector can be used for row and column syndromes, even though a three-block-deep pipeline is used. Only one memory access cycle is required during column-syndrome generation for each row, even though two or more column syndromes are simultaneously generated. Pipelined registers for the intermediate syndrome bytes in the column-syndrome generator allow syndrome-calculation circuits to be shared for all column syndromes.

Dual-column syndrome generation for DVD error correction using an

An architecture that utilizes the cross-check code associated with the error correction code in a data communications system as a data integrity code to protect data stored in a temporary storage buffer within a data channel. In a preferred embodiment, a cross-check encoder and comparison circuit is added to an interface circuit which receives data from a host processing system. Incoming host data is encoded to produce redundant information according to the same Reed-Solomon code implemented in the cross-check circuitry already provided in the data path to detect miscorrections by the error correction code. Cross-check redundancy generated by the interface cross-check encoder is appended to its associated data block in the block memory buffer. The integrity of the data blocks passing through the buffer is checked by utilizing the cross-check circuitry to regenerate the redundant cross-check bytes and then performing a comparison of the regenerated cross-check bytes with the cross-check bytes from the buffer. A similar process is repeated in the reverse path when the data blocks are recovered from a storage medium and delivered to the host through a path that includes the buffer.

Method and apparatus to protect data within a disk drive buffer

A synchronous DMA burst transfer method is provided for transferring data between a host device and a peripheral drive device connected by an ATA bus. The method provides synchronous data transfer capability in an asynchronous system by having one device in charge of both a strobe signal and a data signal. When a host read or write command is delivered to the peripheral drive device, the peripheral device decides when to start the synchronous DMA burst. For a read command, the peripheral device requests the synchronous DMA burst then drives a data word onto the ATA bus after the host acknowledges that it is ready to begin the burst. After allowing time for the data signal to settle, the peripheral device toggles a strobe signal from a high state to a low state. The host sees the edge of the strobe signal at which time the host latches the data word on the bus. Additional data words can be driven on the bus and the strobe signal can be retoggled to latch the additional data words into the host. After all data words have been transferred, the strobe signal is returned to a high state so that it is ready to be used for another host command. By having the device which is sending the data in charge of both the strobe signal and the data signal, the method reduces timing delays and provides a data transfer rate up to 33 MBytes/sec. The method is easily implemented in existing systems and is backward compatible with existing transfer protocols.

Synchronous DMA burst transfer protocol having the peripheral device

An adaptive filter for use in disk drive systems includes coefficient adaptation circuitry operating at a slower rate than the filter and consequently at a reduced power level. The adaptive filter receives input data samples corresponding to raw data read from a disk in the disk drive system and converted to digital form and provides processed output data samples. The action of the filter is defined by characteristic filter coefficients having values that are updated by adaptation circuitry during the operation of the filter. The adaptive filter is independently clocked from the adaptation circuitry, such that the input data samples and the processed output data samples are clocked through the adaptive filter at a clock rate 1/T, and the filter coefficients are updated according to a prescribed algorithm at an update rate slower than the 1/T clock rate. Filter coefficient updating occurs preferably at a rate equal to 1/J, where J is an integer greater than unity and generally in the range of 2 to 8. The coefficient update rate is achieved by providing a separate filter coefficient adaptation clock derived from the system clock by dividing that clock by a user-programmable parameter J. This process reduces the coefficient update rate, which in turn reduces the switching frequency of the logic gates, the number of pipeline latches, and, ultimately, the power consumption.

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San Jose, CA, United States of America

Hung C Nguyen