Lsi Logic Corporation

Lsi Corporation

Hunaid Hussain

Pradipta Ghosh

Arun K Gunda

Saket K Goyal

A library useable to facilitate testing of IO cells of an ASIC. The library includes IO cell identifications and test structures associated with the IO cell identifications, and identifies which test structures are required to test which IO cells. Preferably, the library forms part of an ASIC design system. A method of testing IO cells of an ASIC is also provided, and includes using the library to determine which test structures to use to test the IO cells, and testing the IO cells using the test structures.

Extensible IO testing implementation

A method is provided for analyzing a test vector for use in measuring static current consumed by an integrated circuit that has an embedded memory device. According to the method, a potential test vector is applied to a functional model of the integrated circuit. The logic states of various nodes in the integrated circuit are detected in response to the potential test vector. At least some of the nodes correspond to the input address bits of the memory device, where the memory device has a valid address range on the input address bits. An output is produced for the potential test vector based on whether these logic states correspond to an address within the valid address range.

Method of analyzing static current test vectors for semiconductor integrated circuits

A method and apparatus are provided for analyzing test vectors for use in measuring static current consumed by an integrated circuit. A netlist of interconnected cells is read to identify cell types used within the netlist, wherein the netlist includes a plurality of nodes. Once the netlist has been read, cell characteristics for selected ones of the cell types are read from a technology library to identify pins of the selected cell types to be monitored. The nodes in the netlist that correspond to these pins are identified and are added to an list file. Once the list file has been generated, a computer simulation program is used to simulate a steady-state response of a functional model of the integrated circuit to a potential test vector and to output the resulting logic states on the nodes provided in the list file.

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Milpitas, CA, United States of America

Hunaid Hussain