Stats Chippac Pte. Ltd.

Hun Teak Lee

Jong Kook Kim

Ki Youn Jang

Byung Joon Han

SungWon Cho

ChulSik Kim

Yaojian Lin

Il Kwon Shim

Sungsoo Kim

DeokKyung Yang

In Sang Yoon

KyoungHee Park

Tae Keun Lee

SeungYong Chai

Soo Jung Park

KyoWang Koo

HeeSoo Lee

Jason Seungjoo Lee

Seong Won Park

Kwang Soon Hwang

Rajendra D Pendse

HeeJo Chi

KyungOe Kim

YoungChul Kim

Koo Hong Lee

Youngcheol Kim

MinJung Kim

Byoung Wook Jang

JoonYoung Choi

DaeWook Yang

Yeongbeom Ko

GwangTae Kim

WoonJae Beak

ChangHwan Kim

ByungHyun Kwak

Hyunll Bae

Chul Sik Kim

An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Integrated circuit packaging system with shielding and method of manufacture thereof

Integrated circuit packaging system with shielding and method of manufacturing thereof

A system and method of manufacture of an integrated circuit packaging system includes: a copper film; a first metal layer directly on the copper film; an insulation layer directly on and over the first metal layer, the insulation layer having a via hole through the insulation layer; a conductive via within the via hole and directly on the first metal layer; a second metal layer directly on the conductive via and the insulation layer; a copper post directly on the copper film; a solder pad over the copper post; and an interposer coupled to the copper post and the solder pad.

Integrated circuit packaging system with plated copper posts and method of manufacture thereof

An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.

Integrated circuit packaging system with surface treatment and method of manufacture thereof

In a semiconductor assembly having stacked elements, discrete bumps made of a polymer such as an electrically nonconductive epoxy are interposed between the upper surface of a substrate and the lower surface of the overhanging part of an elevated element (die or package) with the discrete bump directly under bond sites on the elevated element.

Epoxy bump for overhang die

A method of manufacture of an integrated circuit packaging system including: heating a support structure having a conductive pad and an organic surface protection layer on the conductive pad; removing the organic surface protection layer from the conductive pad by a plasma process with a two-step method, the two-step method includes a first step with a dioxygen and a second step with a dihydrogen, wherein the second step immediately follows the first step; and forming an underfill over the conductive pad.

Method of manufacture of integrated circuit packaging system with plasma processing

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Stackable integrated circuit package system

A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.

Integrated circuit packaging system with ultra-thin chip and method of manufacture thereof

A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.

Semiconductor system with fine pitch lead fingers and method of manufacturing thereof

An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.

Inter-stacking module system

A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates

A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.

Semiconductor package system with fine pitch lead fingers and method of manufacturing thereof

A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.

Method of manufacturing a semiconductor package with fine pitch lead fingers

Growing community of inventors

Ichon, South Korea

Hun Teak Lee