Texas Instruments Corporation

University of Michigan

University of California

Hun-Seok Kim

Patrick W Bosshart

Manish Goel

David Theodore Blaauw

David D Wentzloff

Seok-Jun Lee

Dennis Sylvester

Li-Xuan Chuo

Anand Ganesh Dabak

Anuj Batra

Krishnaswamy Nagaraj

Jing-Fei Ren

Sandeep Bhadra

Weijun Zhu

Benjamin Kempke

Babak Daneshrad

Xiao Pu

Aman A Kokrady

Cynthia Anne Chestek

Paras Patel

Taekwang Jang

Michael Barrow

Avish Kosari

Samuel Nason

Eric P Kim

Karim Mohammed

Chin-Wei Hsu

Mingyu Yang

Jamie Phillips

Jaeho Im

Jongyup Lim

Eunseong Moon

Ziyun Li

Julianna Richie

A mote includes an optical receiver that wirelessly receives a power and data signal in form of NIR light energy within a patient and converts the NIR light energy to an electrical signal having a supply voltage. A control module supplies the supply voltage to power devices of the mote. A clock generation circuit locks onto a target clock frequency based on the power and data signal and generates clock signals. A data recovery circuit sets parameters of one of the devices based on the power and data signal and a first clock signal. An amplifier amplifies a neuron signal detected via an electrode inserted in tissue of the patient. A chip identifier module, based on a second clock signal, generates a recorded data signal based on a mote chip identifier and the neuron signal. A driver transmits the recorded data signal via a LED or a RF transmitter.

Wireless neural recording devices and system with two stage RF and NIR power delivery and programming

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Carrier and sampling frequency offset estimation for RF communication with crystal-less nodes

A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Packet processing match and action unit with configurable memory allocation

An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Openflow match and action pipeline structure

A system is presented for non-line-of-sight localization between RF enabled devices. A transmitting node is configured to transmit an RF ranging signal at a first carrier frequency, where the RF ranging signal is modulated with a symbol. The reflecting node is configured to receive the RF ranging signal and further operates to convert the RF ranging signal to a second carrier frequency and retransmit the converted ranging signal while simultaneously receiving the RF ranging signal. The localizing node is configured to receive the converted ranging signal from the reflecting node. The localizing node operates to identify, in frequency domain, the symbol in the converted ranging signal and compute a distance between the reflecting node and the localizing node based in part on the identified symbol in the converted ranging signal. The transmitting node and the localizing node may be on the same or different devices.

Low-power, long-range RF localization system and method

A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Packet processing match and action unit with stateful actions

An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 &#x3bc;W with a sensitivity of &#x2212;72 dBm at a BER of 10and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Low-power receiver for FSK back-channel embedded in 5.8GHz Wi-Fi OFDM packets

Optical flow is measured between a first image and a second image by evaluating a match quantifying parameter in respect of a set of candidate flow vectors. The set of candidate flow vectors includes one or more flow vectors selected in dependence upon one or more neighbor flow vectors associated with one or more neighboring pixels to the given pixel which have previously calculated respective match quantifying parameters indicative of closest matches for the one or more neighboring pixels. The set of candidate flow vectors also includes adjacent flow vectors corresponding to target pixels surrounding the target pixels identified by the neighbor flow vectors. One or more randomly selected random flow vectors is also added to the set of candidate flow vectors. The calculated match quantifying parameters are weighted in dependence upon whether the corresponding candidate flow vector is similar to any other candidate flow vector.

Optical flow measurement

A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

Low power high gain radio frequency amplifier for sensor apparatus

An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Packet processing match and action unit with a VLIW action engine

A digital quadrature architecture is presented that employs switched current digital power amplifiers and uses a digital class-B input code profile in combination with non-overlapping LO signals to overcome the low efficiency problems of conventional quadrature architectures. By employing digital class-B signals, the number of I/Q cells is reduced to half and the need for extra processing of the sign bits is eliminated in the transmitters, thereby improving the efficiency.

Digital quadrature transmitter with class-B I/Q cell sharing

A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Packet processing match and action unit with configurable bit allocation

Growing community of inventors

Dallas, TX, United States of America

Hun-Seok Kim