Samsung Electronics Co., Ltd.

Hun-Kyo Seo

Ki-jae Song

Jae-Hoon Jeong

Chang-Woo Ko

Jae-il Lee

Jong-won Han

Jang-Sun Kim

Soon-Geol Hwang

Jong-Pil Park

A contact apparatus includes a pusher having first and second surfaces, the first surface being connected to a pressure unit, stoppers protruding from edges of the second surface of the pusher away from the pressure unit, a pusher block having first and second surfaces facing each other, the first surface facing the pusher, and the second surface being connected to a semiconductor device, coupling members connecting the pusher to the pusher block, and a connector disposed between the pusher and the pusher block, at least part of a surface of the connector being circular, and the circular surface making a point contact with the pusher or the pusher block.

Contact apparatus and semiconductor test equipment using the same

An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals.

Apparatus for testing a semiconductor device and method of testing a semiconductor device

In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

Package test devices having a printed circuit board

A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

Connecting unit to test semiconductor chips and apparatus to test semiconductor chips having the same

Method of designing a printed circuit board

A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.

Growing community of inventors

Asan-si, South Korea

Hun-Kyo Seo