Samsung Electronics Co., Ltd.

Hun-Hyeoung Leam

Jung-Hwan Kim

Woong Hee Lee

Seok-Woo Nam

Young-sub You

Yong-Seok Kim

Tae-Hyun Kim

Tea-Kwang Yu

Hyun Namkoong

Sang-Hoon Lee

Jai-Dong Lee

Ki-Su Na

Jung-Geun Jee

Won-Jun Jang

Young-Seok Kim

Bon-Young Koo

Chul-Sung Kim

Young-jin Noh

Bong-Hyun Kim

Sang-Hun Lee

Jung-Hyun Park

Hyeon-Deok Lee

Woo-Sung Lee

Yong-Woo Hyung

Jae-Chul Lee

Sang-Kyoung Lee

Seung-Mok Shin

Yong-Sun Lee

Cheol-Kyu Yang

Young-Sub You

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Semiconductor device and method of fabricating the same

In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.

Method of forming an insulation structure and method of manufacturing a semiconductor device using the same

In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.

Methods of forming void-free layers in openings of semiconductor substrates

In an embodiment, a method of forming a gate structure for a semiconductor device includes forming a preliminary gate structure on a semiconductor substrate. The preliminary gate structure includes a gate oxide pattern and a conductive pattern sequentially stacked on the substrate. Then, a re-oxidation process is performed to the substrate having the preliminary gate structure using an oxygen radical including at least one oxygen atom, so that an oxide layer is formed on a surface of the substrate and sidewalls of the preliminary gate structure to form the gate structure for a semiconductor device. The thickness of the gate oxide pattern is prevented from increasing, and the quality of the oxide layer is improved.

Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device

Disclosed herein is a method of forming a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation (SA-STI) structure. First, a tunnel oxide layer is formed on a semiconductor substrate having a SA-STI structure. Next, a first floating gate layer is formed on the tunnel oxide layer at a first temperature of no less than about 530&#xb0; C. A second floating gate layer is then formed on the first floating gate layer at a second temperature of no more than 580&#xb0; C. After depositing the first floating gate layer, the second floating gate layer is in-situ deposited to prevent the growth of a native oxide layer on the surface of the first floating gate layer. Thus, gate resistance can be reduced and process time can be shortened.

Floating gate memory device and method of manufacturing the same

Growing community of inventors

Yongin-si, South Korea

Hun-Hyeoung Leam