Samsung Electronics Co., Ltd.

Hun-Dae Choi

Hangi Jung

Han-gi Jung

Juho Jeon

SukYong Kang

Young-chan Jang

Young-kwon Jo

Ju-Ho Jeon

Hwapyong Kim

Jae-Hun Jung

In-Dal Song

Wangsoo Kim

Yoo-Chang Sung

Junsub Yoon

Ju Ho Jeon

Jinhyeok Baek

Kyoung-Su Lee

Hwa-Pyong Kim

Ga Ram Choi

Suk Yong Kang

Kiduk Park

Cheongryong Cho

In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

Delay locked loop including replica fine delay circuit and memory device including the same

A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided. The clock correction circuit comprises a delay-locked loop circuit configured to receive a first clock signal and generate a second clock signal obtained by delaying the first clock signal; a first duty cycle correction circuit configured to receive the second clock signal and generate a first correction clock signal obtained by correcting a duty cycle of the second clock signal; and a duty cycle detection circuit which includes a second duty cycle correction circuit and an error code generation circuit, wherein the error code generation circuit receives the first correction clock signal, and generates a first error code as to whether to correct the duty cycle of the second clock signal on the basis of the first correction clock signal, the second duty cycle correction circuit generates a second correction clock signal obtained by correcting the duty cycle of the first correction clock signal in response to the first error code, the error code generation circuit generates a second error code as to whether to correct the duty cycle of the second clock signal on the basis of the second correction clock signal, and the first duty cycle correction circuit receives the second error code, and generates a third correction clock signal obtained by correcting the duty cycle of the second clock signal in response to the second error code.

Clock correction circuit and memory system comprising the clock correction circuit

Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Semiconductor memory device and operating method of semiconductor memory device to reduce duty errors

The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

Semiconductor memory device and memory system having the same

A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

Memory device including common mode extractor

Semiconductor memory device and operating method of semiconductor memory device

A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.

Calibration circuit including common node shared by pull-up calibration path and pull-down calibration path, and semiconductor memory device including the same

A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

Delay-locked loop circuit, semiconductor memory device, and methods of operating delay-locked loop circuit

A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Memory device and method of operating the same for latency control

A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Delay locked loop to cancel offset and memory device including the same

A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Memory device including a delay locked loop and operating method of the memory device

An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Electronic circuits for outputting post emphasis signals

Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

Delay-locked loop circuit and semiconductor memory device including the same

A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first die may be configured to perform a first calibration operation using the resistor in response to a ZQ calibration command applied from outside of the memory device. The first die may be configured to generate a ZQ flag signal after the first calibration operation ends and perform a second calibration operation. The second die may be configured to perform the first calibration operation in response to the ZQ flag signal and perform a second calibration after the first calibration operation of the second die ends.

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Seoul, South Korea

Hun-Dae Choi