Fujian Jinhua Integrated Circuit Co., Ltd.

Huixian Lai

Chao-Wei Lin

Yu Cheng Tung

Chiayi Chu

Yu-Cheng Tung

Yifei Yan

Yi-Wang Jhan

Chia-Yi Chu

Fu-Che Lee

An-Chi Liu

Gang-Yi Lin

Qinfu Zhang

Jen-Kuo Wu

Chung-Yen Chou

Chih-Yuan Chen

Jen-Chieh Cheng

The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and at least one second word line arranged by a second pitch, and the second pitch is greater than the first pitch.

Semiconductor device and method of fabricating the same

The invention provides a memory and a forming method thereof. By connecting two node contact parts filled in two node contact windows at the edge and adjacent to each other, a large-sized combined contact can be formed, so that when preparing the node contact parts, the morphology of the combined contact at the edge position can be effectively ensured, and under the blocking protection of the combined contact with a large width, the rest of the node contact parts can be prevented from being greatly eroded, and the morphology accuracy of the independently arranged node contact parts can be improved, thereby being beneficial to improving the device performance of the formed memory.

Memory device and manufacturing method thereof

A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Semiconductor device with shallow trench isolation having multi-stacked layers and method of forming the same

The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

Semiconductor memory device having plug and wire

The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Semiconductor device and method of forming the same

A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer () having an upper portion () and a lower portion (). The upper portion () is multi-layer structure having an increased thickness without changing a thickness of the lower portion (). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion () designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion. In this way, current leakage between word lines (WL) and the active areas (AA) can be mitigated.

Transistor, memory and method of forming same

Shallow trench isolation structure and semiconductor device with the same

Semiconductor memory device

The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.

A shallow trench isolation structure and a semiconductor device. The shallow trench isolation structure includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

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Jinjiang, China

Huixian Lai