Sandisk Technologies Inc.

Huiwen Xu

Bo Lei

Jun Wan

Deepanshu Dutta

Zhenni Wan

Nidhi Agrawal

The adaptive erase scheme includes erasing the memory cells of a selected memory block in at least one erase loop. During the at least one erase loop, simultaneously, an erase voltage is applied to a plurality of channels in the selected memory block, a first bias voltage is applied to the plurality of word lines of the first sub-block, and a second bias voltage is applied to the plurality of word lines of the second sub-block. The first bias voltage is different than the second bias voltage so that the memory cells of the first and second sub-blocks are erased at different speeds.

Adaptive erase scheme for a memory device

A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

Non-volatile memory with erase depth detection and adaptive adjustment to programming

An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Smart early detection of wordline-memory hole defects with wordline-dependent dual sensing during erase verify

The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

Variable programming voltage step size control during programming of a memory device

The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Techniques for reading memory cells in a memory device during a multi-pass programming operation

A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Multi-pass programming operation sequence in a memory device

Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.

Dynamic sense node voltage to compensate for variances when sensing threshold voltages of memory cells

Apparatuses and techniques are described for optimizing a program operation in a memory device in which groups of memory cells are programmed from checkpoint states to respective data states. In a first program pass, groups of memory cells are programmed to respective checkpoint states with verify tests. Each checkpoint state is associated with a set of data states. In a second program pass, the memory cells are programmed closer to their assigned data state with a specified number of program pulses. In a third program pass, the memory cells are programmed to their assigned data state by applying program pulses and performing verify tests. The number of checkpoint states and the number of data states associated with each checkpoint state can be optimized based on a spacing between the verify voltages of the data states.

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Cupertino, CA, United States of America

Huiwen Xu