Synopsys, Inc.

Huiping Huang

Mayukh Bhattacharya

Jonti Talukdar

Shan Yuan

Antony Fan

Chih-Ping Antony Fan

Amelia Huimin Shen

Vinay Nulkar

A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

Measuring device defect sensitization in transistor-level circuits

A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

Fast and scalable methodology for analog defect detectability analysis

A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Visual representation of circuit related data

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Pleasanton, CA, United States of America

Huiping Huang