Montage Lz Technologies (chengdu) Co., Ltd.

Huimin Mao

Shunlin Li

Chengqiang Liu

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: generating, by an Universal Verification Methodology test instance, constrained random parameters and random controls, and storing them to a storage area of a bus function model unit; reading, by a software test instance, the random parameters and the random controls through the central processing unit, and configuring a test of the system on chip; storing execution status information of the software test instance in the storage area; reading, by the Universal Verification Methodology test instance, the execution status information, and adjusting constraint condition for generating random parameters and random controls based on the execution status information to exclude having been tested scenarios, and converting the execution status information into coverage data for coverage analysis.

Verification platform for system on chip and verification method thereof

The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

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Chengdu, China

Huimin Mao