Hong Kong Applied Science and Technology Research Institute Company, Limited

Johnson Electric International Ag

Huimin Guo

Yat Tung Lai

Gang Qian

Wai Po Wong

Lu Chen

Ken Wong

Kam Chuen Wan

Chiping Sun

Shujuan Huang

Wuxue Ni

Shuzuo Lou

Wenchao Wu

Zhongliang Zhou

Chun Kit Lau

Yujian Han

Kai Cheung Chung

A swallowable capsule has a primary magnet along a long axis that aligns between movable electromagnets in a magnetic endoscopy machine. A flip magnet is orthogonal to the long axis. The capsule is rolled around the long axis to flip orientation of a side camera on a side of the capsule. An external base electromagnet below the patient's feet is energized to roll the capsule. The base magnet acts on the flip magnet but not on the orthogonal primary magnet when the long axis is orthogonal to a magnetic axis of the base electromagnet. Most components such as a controller, the side camera, a side laser, batteries, and an antenna, are mounted to a long Printed Circuit Board (PCB) along the long axis, while a front camera and laser are mounted to a front PCB that is mounted orthogonally to a front edge of the long PCB.

Dual-beam dual-magnet capsule for endoscopy in stomach

An On-Off Shift Keying (OOK) receiver has non-continuous Automatic Gain Control (AGC) that sets gain at the beginning of each frame and locks the gain setting for the remainder of the frame, preventing OOK data from causing AGC loop instability. An AGC controller initializes to maximum the gain settings for a Low-Noise Amplifier (LNA), Low-Pass Filter (LPF), and a Programmable Gain Amplifier (PGA) in series that power a rectifier generating a voltage output to a 1/0 data decision circuit. A level detector compares the voltage output to two thresholds. When both thresholds are exceeded, the AGC controller steps down gain settings until the voltage output is between the two thresholds, when the gain settings are locked for the remainder of the current frame. A frame detector resets the AGC controller between frames when a long series of 0 data between frames is detected. LNA gain is reduced last.

Automatic Gain Control (AGC) for On-Off Shift-Keying (OOK) receiver

A voltage detector has a diode ladder with one or more diodes connected in series between a battery voltage input and an upper measuring node. A measuring diode is connected between the upper measuring node and a lower measuring node. A resistor and a power-down switch are connected in series between the lower measuring node and a ground. An analog input to an Analog-to-Digital Converter (ADC) is connected by a switch to the upper measuring node to generate an upper digital value. Then the switch connects the analog input to the lower measuring node to generate a lower digital value. The difference between the upper and lower digital values is the diode voltage drop across the measuring diode and is multiplied by a number of diodes in the diode ladder and added to the upper digital value to generate a battery voltage measurement.

Low-power voltage detector for low-voltage CMOS processes

A switch-less transceiver has parallel LC resonances that act as OFF switches and series LC resonances act as ON switches when resonating at the transmit (TX) or receive (RX) frequency. When the transmitter is disabled, no current flows through series LC filters. Instead, series impedances to ground provide an RF ground to the transmitter output node. A TX inductor between the transmitter output node and the antenna is in parallel with a TX blocking capacitor to ground, which together form a parallel resonance to ground that has a high impedance when resonating at the receiver frequency. This high impedance acts as an OFF switch to block antenna signals from entering the transmitter. The two paths are in parallel, presenting a high impedance to the antenna and forming an OFF switch when the receiver is disabled.

Switch-less connection for radio-frequency (RF) transceivers

A RC oscillator comprises a resistor unit. The resistor unit can comprise at least one set of compensation resistor. Each set of compensation resistor comprises a positive temperature coefficient resistor and a negative temperature coefficient resistor coupled in series with the positive temperature coefficient resistor.

RC oscillator, motor-driven integrated circuit, and motor device

An RC oscillator has a variable capacitor that sets the output frequency. The variable capacitor has m binary-weighted switched capacitor arrays, and each binary-weighted switched capacitor array has binary-weighted capacitors. p binary bits are decoded into an m-bit thermometer code that selects one of the m binary-weighted switched capacitor arrays to use n binary bits to switch its binary-weighted capacitors. Other binary-weighted switched capacitor arrays have all their capacitors switched on, or all their capacitors switched off by the thermometer code. The smallest or unit capacitance of each binary-weighted switched capacitor array is adjusted to compensate for the non-linear reciprocal relationship of frequency being proportional to 1/RC. The unit capacitance is increased for each successive binary-weighted switched capacitor array to reset to the ideal linear relationship of the (p,n)-bit code to frequency.

RC oscillator that uses thermometer codes to select a sub-array and binary codes to select capacitors or resistors within a sub-array for linear and monotonic tuning

A hybrid Analog-to-Digital Converter (ADC) has multiple stages. A first stage and a final stage each use a Successive-Approximation Register (SAR) ADC to generate the Most-Significant-Bits (MSBs) and the Least-Significant-Bits (LSBs) over successive internal cycles. Middle stage(s) use a faster flash ADC with multiple comparators in parallel to generate the middle binary bits, which are then re-converted by a Digital-to-Analog Converter (DAC) and subtracted from the stage's input analog voltage to generate a difference that is amplified by a residual amplifier that outputs an amplified voltage to the next stage. The first stage also has this multiplying DAC structure to convert the MSBs to an amplified voltage to the first of the middle stages. Finally, digital error correction logic removes redundant binary bits between stages. Initial and final SAR stages of 4 and 8 bits with a 4-bit middle stage provide a hybrid ADC of 14-bit precision.

Multi-stage hybrid analog-to-digital converter

This invention provides a multi-stage amplifier incorporating DC offset cancellation. The amplifier has a plurality of series-connected gain stages each of which comprises a differential amplifier unit generating a pair of differential outputs from a pair of differential inputs. In particular, a trailing stage in the plurality of gain stages comprises a digital DC offset cancellation module configured to compensate for a DC offset of the trailing stage's differential amplifier unit. The digital DC offset cancellation module comprises a comparator coupled to the pair of differential outputs of the trailing stage's differential amplifier unit for receiving such differential outputs as inputs for the comparator. Preferably, the comparator has an inherent DC offset that is substantially small. It is preferable that a non-trailing stage of the amplifier comprises an analog DC offset cancellation module for compensating for a DC offset of the non-trailing stage.

DC offset cancellation for a multi-stage amplifier

There is provided an integrated circuit having a programmable gain amplifier and an embedded filter. The programmable gain amplifier and the filter comprise a gain element having an inverting input for receiving an input and a feedback signal, a non-inverting input coupled to ground, and an output. The gain element also has one or more feedback loops coupling the output of the gain element to the inverting input of the gain element. Each feedback loop has a switch coupled in series with at least one passive component. Each switch has a first state to connect the corresponding feedback loop and a second state to disconnect the corresponding feedback loop. Each switch is programmatically configurable to provide a first gain and a first bandwidth and a second gain and a second bandwidth such that the first bandwidth is substantially equal to the second bandwidth.

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Huimin Guo