Intel Corporation

Huimin Chen

Kok Hong Chan

Howard L Heck

Duane G Quiet

Robert A Dunstan

Karthi R Vadivelu

Abdul Rahman Ismail

Dennis Bell

Andrew W Martwick

Yong Yang

David J Harriman

Amit Kumar Srivastava

Thomas A Tetzlaff

Christopher Hull

Udaya S Natarajan

Chunyu Zhang

Dmitriy Berchanskiy

Paul S Durley

Naveed Khan

Travis T Schluessler

Kai Xiao

Andrew M Volk

Selvakumar Panneer

Gary A Solomon

Steven Bernard McGowan

Ken Drottar

Ronald W Swartz

Vui Yong Liew

Zhengmin Li

Raul N Gutierrez

Jingbo Li

Vinay Raghav

Terry L Baucom

Keith A Jones

Amir Bashir

Chunfei Ye

Jia Jun Lee

Abdul Hawk Ismail

John L Baudrexl

Hsiao-Ping Tsai

Vishnu Balraj

Tony L Lewis

Kian Leong Phang

Tim McKee

Kok Hong Chang

Marko Balogh

Teong Guan T G Yew

A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

Per-lane power management of bus interconnects

In one embodiment, an apparatus includes: a transmitter to receive application-specific data and protocol information and to send the application-specific data and the protocol information to a destination circuit via a link; and a protocol engine coupled to the transmitter, where the protocol engine is to cause the transmitter to send the application-specific data according to a first bit error rate (BER) and send the protocol information according to a second BER, the first BER greater than the second BER. Other embodiments are described and claimed.

System, apparatus and method for communicating with a variable bit error rate

Methods and apparatus for adaptive termination calibration of high-speed links. The methods provide a novel termination calibration obtained in conjunction with link training without using an external reference under which the termination resistors for transmitters (Rtx) and receivers (Rrx) are calibrated to the real channel impedance as part of the link training. The techniques may be implemented to optimize high-speed link operation in terms of impedance match between a channel's characteristic impedance and the source termination of a transmitter and the receiver termination of a receiver. During link training, both Rtx and Rrx are adjusted to maximize a peak amplitude of a received signal. Under one approach for bi-directional links, the Rrx for the receivers at both ends of the link are calibrated substantially concurrently. Under another approach, a calibrated Rrx for a first receiver is used for calibrating the Rrx for the second receiver. An Rtx may be set equal to an calibrated Rrx or may be calibrated separately.

Method of adaptive termination calibration

Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

Method of encoding data

Embodiments of the present disclosure are directed toward a universal serial bus (USB) device and a USB host controller. The USB device and USB host controller may be configured to couple to one another via a USB link that may include a high-speed data line and a low-speed data line. The USB device may then transmit, via the high-speed data line, an indication of a digital image to the USB host controller. Other embodiments may be described and/or claimed.

High bandwidth universal serial bus (USB) camera

An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.

Mechanism of power delivery on an asymmetrical dual simplex link

An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

Power management of re-driver devices

Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.

Power state management for lanes of a communication port

Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.

Device, method and system for performing closed chassis debug with a repeater

An apparatus may comprise a port to couple to a plurality of communication paths comprising a first, second, third, and fourth communication path, the communication paths each having a direction of either a receive path or a transmit path, the communication paths comprising a first communication path having a direction that may be selectively configured as a receive path or a transmit path. The apparatus further comprises a controller comprising circuitry, the controller to in response to a communication path reconfiguration command, reconfigure the direction of the first communication path such that the first communication path, second communication path, and third communication path have the same direction and the fourth communication path has a direction opposite to the direction of the first, second, and third communication paths.

Dynamic asymmetric communication path allocation

An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

Two-wire link for time-multiplexed power and data transmission to multiple devices

A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Digital interconnects with protocol-agnostic repeaters

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Portland, OR, United States of America

Huimin Chen