Chinese Academy of Sciences

International Business Machines Corporation

Other

Chartered Semiconductor Manufacturing Ltd (corporation)

Advanced Micro Devices Corporation

Sunovel Suzhou Technologies Ltd.

Globalfoundries Inc.

Beijing Superstring Academy of Memory Technology

Beijing Nmc Co., Ltd.

Huilong Zhu

Zhijiong Luo

Haizhou Yin

Qingqing Liang

Bruce Bennett Doris

Huicai Zhong

Oleg Gluschenkov

Haining S Yang

Dureseti Chidambarrao

Ying Di Zhang

Huajie Chen

Omer H Dokumaci

Zhengwen O Li

Chao Zhao

Huaxiang Yin

Philip Joseph Oldiges

Effendi Leobandung

Qiuxia Xu

Jun Luo

Mukta G Farooq

Xinlin Wang

Kangguo Cheng

Brian Joseph Greene

Yung Fu Chong

Sunfei Fang

Meikei Ieong

Gregory Gower Freeman

Werner A Rausch

Dapeng Chen

Wenwu Wang

Lawrence Alfred Clevenger

Clement Hsingjen Wann

Cyril Cabral, Jr

Xiangdong Chen

Subramanian Srikanteswara Iyer

Thomas W Dyer

Jochen C Beintner

Byeong Yeol Kim

Kaushik Arun Kumar

Thomas Safron Kanarsky

Mahender Kumar

Carl John Radens

Stephen W Bedell

Geng Wang

Christian Lavoie

Min Yang

Hao Wu

Chun-Yung Sung

Zhibin Ren

Tien-Jen Cheng

Ying Li

Wei Jiang

Anda C Mocuta

Wenjuan Zhu

Judson Robert Holt

Ping-Chuan Wang

Kern Rim

Chengwen Pei

Dominic Joseph Schepis

Herbert Lei Ho

Shreesh Narasimha

Louis Lu-Chen Hsu

Ravikumar Ramachandran

Thomas M Shaw

Xiao Hu Liu

Steven John Koester

Rajarao Jammy

Dae-Gyu Park

Harold John Hovel

Nivo Rovedo

Rainer Klaus Krause

Ian D Melville

Diane Catherine Boyd

William Francis Landers

Yanfeng Wang

Xiaojin Wei

Cung D Tran

Hong Yang

Rajeev Malik

Yaocheng Liu

Anthony K Stamper

Jack Allan Mandelman

Keith Kwong Hon Wong

Katherine Lynn Saenger

Wei He

Babar Ali Khan

Hon-Sum Philip Wong

Michael Jay Shapiro

William K Henson

Abhishek Dube

Xinyu Liu

Stephan Grunow

Jiang Yan

Jay William Strane

David R Hanson

Oliver Desmond Patterson

Xi Li

Chen Bo Li

Kam-Leung Lee

Joyce C Liu

A semiconductor apparatus with an isolation portion between vertically adjacent elements and an electronic device including the semiconductor apparatus are provided. The semiconductor apparatus may include: a substrate; a first vertical semiconductor element and a second vertical semiconductor element stacked on the substrate sequentially, each of the first vertical semiconductor element and the second vertical semiconductor element including a first source/drain region, a channel region and a second source/drain region stacked sequentially in a vertical direction; and an isolation structure configured to electrically isolate the first vertical semiconductor element from the second vertical semiconductor element, and the isolation structure including a pn junction.

Semiconductor apparatus with isolation portion between vertically adjacent elements, and electronic device

Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.

Semiconductor apparatus, manufacturing method therefor, and electronic equipment including the semiconductor apparatus

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

MRAM, method of manufacturing the same, and electronic device including the MRAM

The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.

Semiconductor device and method of manufacturing the same, and electronic apparatus including the semiconductor device

A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Semiconductor device and method of manufacturing the same, and electronic apparatus including semiconductor device

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Semiconductor device, method of manufacturing the same and electronic device including the device

A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Semiconductor memory device, method of manufacturing the same, and electronic device including the same

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Semiconductor device, method of manufacturing the same and electronic device including the same

An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.

Interconnection structure, circuit and electronic apparatus including the interconnection structure or circuit

A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.

Strained vertical channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same

Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. According to the embodiments, the nanowire/nanosheet device may include: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet and a second nanowire/nanosheet, wherein the first nanowire/nanosheet and the second nanowire/nanosheet are spaced apart from a surface of the substrate, the first nanowire/nanosheet and the second nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in a direction parallel to the surface of the substrate; a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet; and a gate stack extending in a second direction intersecting the first direction to surround the first nanowire/nanosheet and the second nanowire/nanosheet.

Nanowire/nanosheet device with support portion, method of manufacturing the same, and electronic apparatus

Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Vertical semiconductor device, manufacturing method therefor, integrated circuit and electronic device

A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Semiconductor device and manufacturing method thereof and electronic apparatus including the same

The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.

Semiconductor device and manufacturing method thereof, and electronic device including the semiconductor device

An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

Interconnection structure and method of manufacturing the same, and electronic device including the interconnection structure

Growing community of inventors

Poughkeepsie, NY, United States of America

Huilong Zhu