Chinese Academy of Sciences

International Business Machines Corporation

Other

Chartered Semiconductor Manufacturing Ltd (corporation)

Advanced Micro Devices Corporation

Sunovel Suzhou Technologies Ltd.

Globalfoundries Inc.

Beijing Superstring Academy of Memory Technology

Beijing Nmc Co., Ltd.

Huilong Zhu

Zhijiong Luo

Haizhou Yin

Qingqing Liang

Bruce Bennett Doris

Huicai Zhong

Oleg Gluschenkov

Haining S Yang

Dureseti Chidambarrao

Ying Di Zhang

Huajie Chen

Omer H Dokumaci

Zhengwen O Li

Chao Zhao

Huaxiang Yin

Philip Joseph Oldiges

Effendi Leobandung

Qiuxia Xu

Jun Luo

Mukta G Farooq

Xinlin Wang

Kangguo Cheng

Brian Joseph Greene

Yung Fu Chong

Sunfei Fang

Meikei Ieong

Gregory Gower Freeman

Werner A Rausch

Dapeng Chen

Wenwu Wang

Lawrence Alfred Clevenger

Clement Hsingjen Wann

Cyril Cabral, Jr

Xiangdong Chen

Subramanian Srikanteswara Iyer

Thomas W Dyer

Jochen C Beintner

Byeong Yeol Kim

Kaushik Arun Kumar

Thomas Safron Kanarsky

Mahender Kumar

Carl John Radens

Stephen W Bedell

Geng Wang

Christian Lavoie

Min Yang

Hao Wu

Chun-Yung Sung

Zhibin Ren

Tien-Jen Cheng

Wei Jiang

Ying Li

Anda C Mocuta

Wenjuan Zhu

Judson Robert Holt

Ping-Chuan Wang

Kern Rim

Chengwen Pei

Dominic Joseph Schepis

Herbert Lei Ho

Shreesh Narasimha

Ravikumar Ramachandran

Louis Lu-Chen Hsu

Thomas M Shaw

Xiao Hu Liu

Steven John Koester

Rajarao Jammy

Dae-Gyu Park

Harold John Hovel

Nivo Rovedo

Rainer Klaus Krause

Ian D Melville

Diane Catherine Boyd

William Francis Landers

Yanfeng Wang

Xiaojin Wei

Cung D Tran

Hong Yang

Rajeev Malik

Yaocheng Liu

Anthony K Stamper

Jack Allan Mandelman

Keith Kwong Hon Wong

Katherine Lynn Saenger

Wei He

Babar Ali Khan

Hon-Sum Philip Wong

Michael Jay Shapiro

William K Henson

Abhishek Dube

Xinyu Liu

Stephan Grunow

Jiang Yan

Jay William Strane

David R Hanson

Oliver Desmond Patterson

Xi Li

Chen Bo Li

Kam-Leung Lee

Joyce C Liu

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory device layer, including a first source/drain region, a second source/drain region and a first channel region; a first gate stack extending vertically to pass through the memory device layer and including a first gate conductor layer and a memory functional layer, and a memory cell is defined at an intersection of the first gate stack and the memory device layer; a selection device layer on the memory device layer, including a third source/drain region, a fourth source/drain region and a second channel region; a second gate stack above the first gate stack and extending vertically to pass through the selection device layer; and a connecting portion electrically connecting the third source/drain region to the first gate conductor layer.

NOR-type memory device, method of manufacturing Nor-type memory device, and electronic apparatus including memory device

A semiconductor device having a zigzag structure, a method of manufacturing the semiconductor device, and an electronic including the semiconductor device. The semiconductor device may include a semiconductor layer () extending in zigzag in a vertical direction with respect to a substrate (). The semiconductor layer () includes one or more first portions disposed in sequence and spaced apart from each other in the vertical direction and second portions respectively disposed on and connected to opposite ends of each first portion. A second portion at one end of each first portion extends from the one end in a direction of leaving the substrate, and a second portion at the other end of the each first portion extends from the other end in a direction of approaching the substrate. First portions adjacent in the vertical direction are connected to each other by the same second portion.

Semiconductor device having zigzag structure, method of manufacturing semiconductor device, and electronic device

Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.

NOR-type memory device, method of manufacturing NOR-type memory device, and electronic apparatus including memory device

A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.

NOR-type storage device, method of manufacturing the same, and electronic apparatus including storage device

A semiconductor apparatus including a capacitor and a method of manufacturing the same, and an electronic device including the semiconductor apparatus are provided. According to embodiments, the semiconductor apparatus may include: a vertical semiconductor device including an active region extending vertically on a substrate; and a capacitor including a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode sequentially stacked. The first capacitor electrode extends vertically on the substrate and includes a conductive material, and the conductive material includes at least one semiconductor element contained in the active region of the vertical semiconductor device.

Semiconductor apparatus including capacitor and method of manufacturing the same, and electronic device

A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.

Metallization stack and method of manufacturing the same, and electronic device including metallization stack

A semiconductor apparatus with an isolation portion between vertically adjacent elements and an electronic device including the semiconductor apparatus are provided. The semiconductor apparatus may include: a substrate; a first vertical semiconductor element and a second vertical semiconductor element stacked on the substrate sequentially, each of the first vertical semiconductor element and the second vertical semiconductor element including a first source/drain region, a channel region and a second source/drain region stacked sequentially in a vertical direction; and an isolation structure configured to electrically isolate the first vertical semiconductor element from the second vertical semiconductor element, and the isolation structure including a pn junction.

Semiconductor apparatus with isolation portion between vertically adjacent elements, and electronic device

Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.

Semiconductor apparatus, manufacturing method therefor, and electronic equipment including the semiconductor apparatus

A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

MRAM, method of manufacturing the same, and electronic device including the MRAM

The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.

Semiconductor device and method of manufacturing the same, and electronic apparatus including the semiconductor device

A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Semiconductor device and method of manufacturing the same, and electronic apparatus including semiconductor device

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Semiconductor device, method of manufacturing the same and electronic device including the device

A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Semiconductor memory device, method of manufacturing the same, and electronic device including the same

A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Semiconductor device, method of manufacturing the same and electronic device including the same

An interconnection structure for semiconductor devices formed on a substrate may be arranged under the semiconductor devices. The interconnection structure includes at least one via layer and at least one interconnection layer alternately arranged in a direction from the semiconductor device to the substrate, wherein each via layer includes via holes respectively arranged under at least a part of the semiconductor devices, and each interconnection layer includes conductive nodes respectively arranged under at least a part of the semiconductor devices, and in a same interconnection layer, a conductive channel is provided between at least one conductive node and at least another node; and the via holes in each via layer and the conductive nodes in each interconnection layer corresponding to the via holes at least partially overlap with each other in the direction from the semiconductor device to the substrate.

Interconnection structure, circuit and electronic apparatus including the interconnection structure or circuit

Growing community of inventors

Poughkeepsie, NY, United States of America

Huilong Zhu