Samsung Electronics Co., Ltd.

Huijung Kim

Kyunghwan Lee

Kiseok Lee

Yongseok Kim

Hyuncheol Kim

Jaeho Hong

Sungwon Yoo

Sangwon Kim

Hyeonjin Shin

Satoru Yamada

Eunkyu Lee

Junsoo Kim

Taejin Park

Minhee Cho

Sangyeon Han

Junhyeok Ahn

Minwoo Kwon

Myeongdong Lee

Yoosang Hwang

Keunnam Kim

Sunghee Han

Sehoon Kim

Jangeun Lee

Hyunmog Park

Sohyun Park

Ilgweon Kim

Inhwan Hwang

Chaehag Yi

Sooyong Kim

Jaehwan Cho

Yunhu Ji

Hyeonje Cho

Inwoo Kim

Sanghoon Kang

Hyeongseok Jeong

A gate structure may include a first gate electrode extending in a first direction, a second gate electrode on a portion of the first gate electrode, a gate mask on the first and second gate electrodes, and a gate insulation pattern on a lower surface and a sidewall of the first gate electrode and sidewalls of the second gate electrode and the gate mask. The gate structure is in an upper portion of a substrate. A grain size of the second gate electrode is greater than a grain size of the first gate electrode.

Gate structures and semiconductor devices including the same

A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

Semiconductor devices including semiconductor pattern

A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

Semiconductor devices having buried gates

An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

Integrated circuit device

A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

Semiconductor device including carbon-containing contact fence

A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

Semiconductor memory device

A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

Semiconductor devices including an edge insulating layer

A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

Memory device having a channel provided on a memory unit

An operation method for reducing energy consumption and an electronic apparatus thereof are provided. The operation method includes obtaining, by the electronic apparatus, weather forecast information, inputting, by the electronic apparatus, the weather forecast information to an artificial intelligence model for predicting an amount of power to be consumed by a first air conditioner, and displaying, by the electronic apparatus, the predicted power consumption amount of the first air conditioner output from the artificial intelligence model, wherein the artificial intelligence model is trained to obtain correlation information between a weather condition and a power consumption amount of an air conditioner, based on a weather history and operations of a plurality of air conditioners related to the weather history, and predict the amount of power to be consumed by the first air conditioner based on the correlation information and the weather forecast information.

Electronic apparatus and operation method for predicting HVAC energy consumption

A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.

Semiconductor devices

A method is provided for operating a radio frequency (RF) receiver including a transimpedance amplifier, a capacitor selectively connected in parallel with the transimpedance amplifier, a channel selection filter unit connected to an output terminal of the transimpedance amplifier, and a variable gain amplification unit selectively connected in parallel with the channel selection filter unit. The method includes measuring signal-to-noise ratio from an output of the RF receiver, and comparing the measured signal-to-noise ratio with a reference signal-to-noise ratio. When the measured signal-to-noise ratio is greater than the reference signal-to-noise ratio, the capacitor is electrically disconnected from being connected in parallel with the transimpedance amplifier and a variation in the measured signal-to-noise ratio is measured. When the measured variation is in tolerance, the channel selection filter is bypassed to select the variable gain amplification unit.

Wireless communication device and method of operating the same

Growing community of inventors

Seongnam-si, South Korea

Huijung Kim