Ningbo University

Huihong Zhang

Pengjun Wang

Yuejun Zhang

Gang Li

Daohui Gong

Xiaotian Zhang

Haizhen Yu

Keji Zhou

Yaopeng Kang

Haiming Zhang

Zhen Li

Yunfei Yu

Haoyu Qian

Shunxin Ye

Kangping Li

The disclosure discloses a method for defending control flow attacks. When a data processor gives a response to an interrupt routine, a return address and a binary key are input to an encryption circuit to be encrypted to obtain an encrypted return address, and the obtained encrypted return address is synchronously written into a stack of the data processor and an built-in register bank; when the response given to the interrupt routine by the data processor is finished, the encrypted return address is read from the tack of the data processor and the built-in register bank; afterwards, the two encrypted return addresses are decrypted by first and second decryption circuits respectively to obtain two decrypted return addresses; and the two decrypted return addresses are compared to draw a conclusion whether the data process suffers from a control flow attack, and data processor determines to continue or terminate the routine accordingly.

Method for defending control flow attacks based on XOR gates

The invention discloses a circuit aging detection sensor based on voltage comparison. A control circuit generates an aging voltage signal, a standard voltage signal and a reference voltage signal. The aging voltage signal passes through a first voltage-controlled oscillator to generate an aging frequency signal. The standard voltage signal passes through a second voltage-controlled oscillator to generate a standard frequency signal. The standard frequency signal and the aging frequency signal pass through an aging detection circuit to generate a frequency difference signal. A level signal generated by a serial data detector passes through a beat-frequency oscillator to generate a reset signal. A counter quantizes aging information, which is converted by a digital-analog converter into a quantized voltage signal. The quantized voltage signal is compared with the reference voltage signal by a voltage comparator, to generate a hopping signal at a voltage superposition node, and an aging signal is output.

Circuit aging detection sensor based on voltage comparison

A domino full adder based on delayed gating positive feedback comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a first inverter, a second inverter, a third inverter and a fourth inverter.

Domino full adder based on delayed gating positive feedback

The disclosure discloses a lookup table-based circuit aging detection sensor, including a control circuit, two voltage controlled oscillators (VCOs), two shaping circuits, a phase comparator, a 3-digit voter, a beat-frequency oscillator, an 8-digit counter, a latch, a lookup table array and a digital-analogue converter. The control circuit respectively connects with the phase comparator, the 3-digit voter, the 8-digit counter, the first and the second VCOs. The first and second VCOs connect with the first and second shaping circuits respectively. The first and second shaping circuits connect with the phase comparator. The phase comparator connects with the 3-digit voter. The 3-digit voter connects with the beat-frequency oscillator. The beat-frequency oscillator respectively connects with the 8-digit counter and the latch. The 8-digit counter connects with the latch. The latch connects with the lookup table array. The lookup table array connects with the digital-analogue converter.

Circuit aging detection sensor based on lookup table

A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

True random number generator based on voltage-controlled oscillator

A positive feedback XOR/XNOR gate and a low-delay hybrid logic adder are provided. The low-delay hybrid logic adder comprises the positive feedback XOR/XNOR gate and an output circuit. The positive feedback XOR/XNOR gate comprises a first PMOS transistor and a second PMOS transistor used as pass transistors, a first NMOS transistor and a second NMOS transistor constituting a pull-down network, and a third PMOS transistor, a third NMOS transistor and a fourth NMOS transistor constituting a positive feedback loop. When an XOR logic output terminal of the positive feedback XOR/XNOR gate is pulled down below a switching threshold of an inverter formed by the third PMOS transistor and the fourth NMOS transistor, the positive feedback loop starts to operate to enable the XOR logic output terminal of the positive feedback XOR/XNOR gate to enter a pull-down phase to be pulled down to a low level to avoid threshold voltage losses.

Positive feedback XOR/XNOR gate and low-delay hybrid logic adder

A multi-port PUF circuit based on MOSFET current division deviations comprises a reference source, a row decoder, a column decoder, a timing controller and 32 PUF arrays. Each PUF array comprises 512 PUF cells arranged in 128 rows and 4 columns, an arbiter, a 1inverter, a 2inverter, a 3inverter, a 4inverter and eight transmission gates. The reference source is connected to the PUF arrays. The moutput terminal of the row decoder is connected to the mrow selective signal input terminals of the 32 PUF arrays. The joutput terminal of the column decoder is connected to the jselective signal input terminals of the 32 PUF arrays. The 1output terminal of the timing controller is connected to the control terminal of the row decoder. The 2output terminal of the timing controller is connected to the control terminal of the column decoder. The multi-port PUF circuit has the advantages of small circuit area and low power consumption while ensuring circuit performance.

Multi-port PUF circuit based on MOSFET current division deviations

Disclosed is a lightweight bistable PUF circuit, comprising a decoding circuit, a timing control circuit, a PUF cell array and n sharing foot circuits. The PUF cell array is formed by m*n PUF cells arrayed in m lines and n columns. Each PUF cell includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, and the four PMOS transistors have the minimum width-to-length ratio of 120 nm/60 nm under a TSMC 65 nm process. Each sharing foot circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first two-input NAND gate and a second two-input NAND gate, and the four NMOS transistors have a width-to-length ratio ranging from 2 um/60 nm to 8 um/60 nm. The lightweight bistable PUF circuit has a reset function and the advantages of small area, low power consumption, small time delay and high speed.

Lightweight bistable PUF circuit

A static memory cell capable of balancing bit line leakage currents is characterized by including a 1PMOS transistor, a 2PMOS transistor, a 1NMOS transistor, a 2NMOS transistor, a 3NMOS transistor, a 4NMOS transistor, a 5NMOS transistor, a 6NMOS transistor, a 7NMOS transistor, an 8NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1NMOS transistor, the 2NMOS transistor, the 3NMOS transistor and the 4NMOS transistor are all normal threshold NMOS transistors. The 1PMOS transistor and the 2PMOS transistor are both low threshold PMOS transistors. The 5NMOS transistor, the 6NMOS transistor, the 7NMOS transistor and the 8NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Static memory cell capable of balancing bit line leakage currents

A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1CNFET transistor, the 2CNFET transistor, the 3CNFET transistor, the 4CNFET transistor, the 5CNFET transistor, the 6CNFET transistor, the 7CNFET transistor, the 8CNFET transistor, the 9CNFET transistor, the 10CNFET transistor, the 11CNFET transistor, the 12CNFET transistor and the 13CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1inverter, the 2inverter, the 3inverter, the 4inverter, the 14CNFET transistor, the 15CNFET transistor, the 16CNFET transistor, the 17CNFET transistor, the 18CNFET transistor and the 19CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Ternary sense amplifier and SRAM array realized by the ternary sense amplifier

A current-mode PUF circuit based on a reference current source comprises an input register, the reference current source, a deviation current comparator and a timing controller. The input register is used for ensuring synchronization of the input challenges to avoid influences of asynchronous challenges on output responses. The reference current source generates a reference current for temperature and voltage compensation. A deviation current source array generates two paths of deviation currents under the control of the input challenges. The deviation current comparator generates and outputs a judgement according to the magnitude of the current provided by the deviation current source array. The timing controller is used for generating timing information for operation of the PUF circuit. The invention has the following advantages: the deviation current source array outputs deviation currents with high robustness and high reliability. Simulation results show that the PUF circuit of the invention has good uniqueness and high reliability of 99.6% when operating under difference temperatures (&#x2212;40&#x2dc;120&#xb0; C.) and different voltages (1.08&#x2dc;1.32V).

Current-mode PUF circuit based on reference current source

The present invention discloses a shift register capable of defending against DPA attack, comprising 4 master-slave D flip-flops, 12 two-input NAND/AND gates, 4 three-input NOR/OR gates and 40 inverters; the 4 master-slave D flip-flops are provided with reset function; it is based on TSMC 65 mm CMOS technique; as indicated by Spectre simulation verification, the shift register of the present invention has correct logic function with NED and NSD below 2.66% and 0.63% respectively under multi PVT combinations, which is provided with significant performance in defense differential power consumption analysis.

Shift register capable of defending against DPA attack

A method for optimizing an area of a ternary FPRM circuit using population migration algorithm, the method including: 1) establishing an area estimation model of the ternary FPRM circuit; 2) establishing a corresponding relationship between the ternary FPRM circuit and population migration algorithm; 3) setting an attraction function for calculating the attraction of the population location in population migration algorithm; 4) setting relevant parameters of population migration algorithm; and 5) employing population migration algorithm to calculate and obtain the greatest attractive site and the greatest attraction.

Method for optimizing area of ternary FPRM circuit using population migration algorithm

The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column decoder, a ternary output circuit and a ternary PUF unit array; the said ternary PUF circuit is arranged into a 3rows&#xd7;3columns matrix formed by 3&#xd7;3ternary PUF units; the ternary PUF unit comprises a 1CNFET transistor, a 2CNFET transistor, a 3CNFET transistor, a 4CNFET transistor, a 5CNFET transistor, a 6CNFET transistor, a 7CNFET transistor, an 8CNFET transistor, a 9CNFET transistor and a 10CNFET transistor; its advantage lies in the fact that it is provided with small circuit area and higher randomness and uniqueness while ensuring proper logic function.

Ternary PUF unit and circuit realized by CNFET

The present invention discloses a multi-port PUF circuit based on NMOS zero temperature coefficient point, comprising an input register, a deviation current source, a arbiter and a disturbing module used to construct a multi-port PUF circuit; the input register comprises m D-flip-flops; the deviation current module comprises m deviation current cells; the arbiter comprises 2n current sensitive amplifiers; the disturbing module comprises n 2-input XOR gates; wherein an input challenge used to configure deviation current generation module can update IDs without replacement of hardware. In addition, it has a capability of producing a multi-bit IDs in one clock cycle. Post-layout simulation results show that the PUF circuit is provided with excellent uniqueness and randomness with reliability up to 98.2% across temperature variation from &#x2212;40&#xb0; C. to 125&#xb0; C., and supply voltage variation from 1.08V to 1.32V; it can be applied in information security field.

Growing community of inventors

Zhejiang, China

Huihong Zhang