International Business Machines Corporation

Huihao Xu

Louis L Hsu

James D Rockrohr

Michael Anthony Sorna

Karl David Selander

Steven John Zier

Jeremy K Stephens

Joseph Natonio

James Stephen Mason

Hayden C Cranford, Jr

Louis C Hsu

Matthew B Baecher

Charlie Chornglii Hwang

Mark R Taylor

Kevin G Kramer

Thomas J Bardsley

Joseph O Marsh

Hibourahima Camara

Harry I Linzer

Philip J Murfet

William F Washburn

Matt R Cordrey-Gale

A design structure embodied in a machine-readable medium used in a design process provides a transmitter having a frequency response controllable in accordance with an operational parameter, and may include a storage operable to store operational parameters for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. A sensor can be used to detect an operating condition. In response to a change in the detected operating condition, a stored operational parameter corresponding to the detected operating condition can be used to control the frequency response of the transmitter.

Design structure for transmitter bandwidth optimization circuit

A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.

Transmitter bandwidth optimization circuit

A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.

Structure for out of band signaling enhancement for high speed serial driver

An integrated microelectronic serial driver is provided which is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.

Out of band signaling enhancement for high speed serial driver

A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor ('NFET') storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.

Structure for robust cable connectivity test receiver for high-speed data receiver

A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.

Robust cable connectivity test receiver for high-speed data receiver

In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.

Automatic adaptive equalization method for high-speed serial transmission link

A system for protecting a weak device operating in micro-electronic circuit and a design structure including the system embodied in a machine readable medium are disclosed. The system includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system further includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

Avoiding device stressing

Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

System and method of digitally testing an analog driver circuit

A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

Front end interface for data receiver

A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.

System of digitally testing an analog driver circuit

A system and method of detecting a fault in a transmission link are provided which includes providing a selectable reference level according to one of a direct current (DC) mode threshold and an alternating current (AC) mode threshold, wherein the DC mode threshold is a fixed potential and the AC mode threshold varies with time. An input signal arriving from the transmission link is compared to one of the DC mode threshold and the AC mode threshold to determine whether a fault is present in the transmission link.

System and method for detecting cable faults for high-speed transmission link

A system for protecting a weak device operating in micro-electronic circuit that includes a high voltage power supply from high voltage over stressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

Method to avoid device stressing

A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

Automatic adaptive equalization method and system for high-speed serial transmission link

Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto. The programmable peaking receiver also includes a pair of tail transistors, coupled to draw current from the input transistors, and a programmably adjustable impedance element coupled between current-conducting nodes of the tail transistors. The impedance of the programmably adjustable impedance element is thereby adjustable in response to programming signal input to adjust a peaking function of the programmable peaking receiver.

Growing community of inventors

Brooklyn, NY, United States of America

Huihao Xu