International Business Machines Corporation

Synopsys, Inc.

Cadence Design Systems, Inc.

Pearl Street Technologies, Inc.

Hui Zheng

Anirudh Devgan

Byron Lee Krauter

Michael Werner Beattie

Tao Lin

Emre Tuncer

Alessandra Nardi

Alfred Wong

Vivek Raghavan

Pramod Thazhathethil

Amir Ajami

Xin Gu

Nityanand Rai

David Bromberg

Marko Jereminov

Kevin Beattie, Legal Representative

Reliable, automated or semi-automated systems/methods that address technical problems involved in electrical power grid design, planning, and operation/control are disclosed. Applications include the technical problem of optimizing adjustments of, and/or infrastructure additions to, large electrical power grids in response to changed operating conditions or planned facility additions that may impact their reliability. An automated or semi-automated system for identifying appropriate adjustments to the electrical power grid and/or addition of new facilities, and the methods and executable computer instructions that enable them, are disclosed.

Systems, methods, and software for identification and application of physical mitigations in planning and operating an electrical power grid

An improved approach is provided for determining differential voltages for driver and receiver pairs as a result of electrostatic discharge (ESD) events including identifying circuits of interest, re-characterizing the circuits of interest into a system for evaluating differential voltages, determining the differential voltages for ESD pin locations, and outputting results after iterating through all the ESD pin locations. In some embodiments, re-characterizing may include performing a resistance only extraction of a net, attaching a resistance to any node in the circuit and to ground, formulating a conductance matrix and distributing the total current I as source points. In some embodiments, determining differential voltages for ESD pin locations may include, stamping a first ESD pin location with a total current, solving for the system using previously computed values, mapping the driver and receiver pairs to the nodes in the system, computing the differential voltage, and recording the lowest differential voltage.

Method and system for efficiently determining differential voltages for electrostatic discharge simulations

The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.

Electrical analysis process

A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Lithography aware leakage analysis

A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.

Lithography aware timing analysis

A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.

Efficient electromagnetic modeling of irregular metal planes

A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.

Compact chip package macromodels for chip-package simulation

A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.

Growing community of inventors

Round Rock, TX, United States of America

Hui Zheng