Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Other

Hui Zang

Ruilong Xie

Min-Hwa Chi

Haiting Wang

Laertis Economikos

Jiehui Shu

Guowei Xu

Tenko Yamashita

Bingwu Liu

Jerome Ciavatti

Hong Yu

Shesh Mani Pandey

Jinping Liu

Scott Beasor

Manfred Eller

Chanro Park

Haigou Huang

Yi Qi

Hsien-Ching Lo

Wei Hong

Yanping Shen

Josef S Watts

Chun-chen Yeh

Lars W Liebmann

Balasubramanian Pranatharthiharan

Daniel Chanemougame

Xusheng Kevin Wu

Zhenyu Hu

Hyun-Jin Cho

Tek Po Rinus Lee

Jae Gon Lee

Jagar Singh

Bipul C Paul

Lei Sun

Youngtag Woo

Chun Yu Wong

Garo Jacques Derderian

Miaomiao Wang

Yongjun Shi

Liu Jiang

Veeraraghavan S Basker

Julien Frougier

Kwan-Yong Lim

Randy W Mann

Wei Zhao

Xuelian Zhu

Rinus Tek Po Lee

Kangguo Cheng

John H Zhang

Chun-Chen Yeh

Daniel J Jaeger

Keith Howard Tabakman

Jin Haeng Cho

Jinsheng Gao

Xiaoqiang Zhang

Min Gyu Sung

Hoon Sik Kim

Guillaume Bouche

Steven J Bentley

Andreas Knorr

George Robert Mulfinger

Jianwei Peng

Steven R Soss

Ajey Poovannummoottil Jacob

Judson Robert Holt

Viraj Yashawant Sardesai

David Paul Brunco

Michael Vincent Aquilino

Jessica M Dechene

Bharat V Krishnan

Moosung M Chae

Qun Gao

Gabriel Padron Wells

Andrew Mark Greene

Xunyuan Zhang

Siva P Adusumilli

Huang Liu

Vimal Kumar Kamineni

Murat Kerem Akarvardar

Jin Ping Liu

Srikanth Balaji Samavedam

Rishikesh Krishnan

Timothy James McArdle

Wenhui Wang

Ravi Prakash Srivastava

Rui Chen

Robert J Miller

Zhiguo Sun

Huy Cao

Xuan Anh Tran

Matthew W Stoker

Xinyuan Dou

Yuping Ren

Tao Han

Qiang Fang

Chih-Chiang Chang

Haifeng Sheng

Halting Wang

Hui Zhan

Bala S Haran

A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Formation of trench silicide source or drain contacts without gate damage

One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Gate contact structures and cross-coupled contact structures for transistor devices

The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

Single diffusion cut for gate structures

The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.

A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

Gate cut isolation including air gap, integrated circuit including same and related method

The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

Scaled gate contact and source/drain cap

A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

Forming two portion spacer after metal gate and contact formation, and related IC structure

A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

Transistor comprising an air gap positioned adjacent a gate electrode

One illustrative integrated circuit (IC) product disclosed herein includes a selection gate electrode and a first gate insulation layer positioned above a substrate and a memory gate electrode positioned above the substrate and adjacent the selection gate electrode, wherein the memory gate electrode comprises a bottom surface and first and second opposing sidewall surfaces. This embodiment of the IC product also includes a plurality of layers of insulating material, wherein a first portion of the layers of insulating material is positioned between the first gate insulation layer and the first opposing sidewall of the memory gate electrode, a second portion of the layers of insulating material is positioned between the bottom surface of the memory gate electrode and the upper surface of the semiconductor substrate, and a third portion of the layers of insulating material is positioned on the second opposing sidewall of the conductive memory gate electrode.

Split gate (SG) memory device and novel methods of making the SG-memory device

The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.

Middle of line structures

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

Electrical fuse formation during a multiple patterning process

The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

Middle of line gate structures

Growing community of inventors

Guilderland, NY, United States of America

Hui Zang